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PREMILINARY - 2/16/00 Version 3
DS3120 28 Channel T1 Framer
www.dalsemi.com
FEATURES
* * * * * * * * * * * * * * * * * 28 T1 DS1/ISDN-PRI/J1 framing transceivers All 28 framers are fully independent Directly supports loop timing & external timing Supports H.100 / MVIP 8 MHz backplanes Frames to D4, ESF, & SLC-96 Transparent framing mode Frame bit clock gapping option Hardware based signaling option Fully independent transmit and receive functionality Integral HDLC controller with 64-byte buffers; configurable for FDL or DS0 operation Generates and detects in-band loop codes from 1 to 8 bits in length DS0 monitor capability Per DS0 channel loopback Software compatible with other Dallas Semiconductor T1 framers 1.8V core supply with 5V tolerant I/O; low power .18 um CMOS 27 mm x 27 mm, 316 lead 1.27 mm pitch PBGA package IEEE 1149.1 support
FUNCTIONAL DIAGRAM
data clock Receive Framer data frame sync clock frame sync data
data
Transmit Formatter 28 T1 Framers
Parallel Control Port
PIN DESCRIPTION
DS3120 - (00 C to 700 C) DS3120N - (-400 C to +850 C)
DESCRIPTION
The DS3120 is a highly dense version of Dallas Semiconductor's popular T1 framer series. It shares the same register structure as the DS2151, DS2152, DS21352, DS21552, DS21Q352, DS21Q552, DS2141A, DS21Q41B, DS21Q42, DS21FT42, and DS21FF42. The DS3120 contains 28 fully independent framers that are configured and read through a common microprocessor compatible parallel port. The device fully meets all of the latest T1 specifications including ANSI T1.403-1999, ANSI T1.231-1993, AT&T TR 62411 (12-90), AT&T TR54016, and ITU G.704 and G.706.
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1. INTRODUCTION
The DS3120 is a highly dense version of the other popular Dallas Semiconductor T1 framers. Due to high density of framers and since the DS3120 is intended to be used primarily in channelized T3 applications, a number of features that are found on Dallas Semiconductor's other T1 framers are not available in the DS3120. These missing features are listed in Table 1-1 below. Please see the separate Application Note for a more complete discussion of missing features and the differences between the DS3120 and other Dallas Semiconductor framers. A list of the main features in the DS3120 is detailed in Table 1-2.
Features Not Available in DS3120 Table 1-1
* * * * No bipolar interface No receive side signaling re-insertion function Limited elastic store functionality Missing signals include RCHBLK, TCHBLK, RCHCLK, TCHCLK, TLINK, TLCLK, RLINK, RLCLK, RMSYNC, RFSYNC, RLOS/LOTC, and FMS
DS3120 Main Features List Table 1-2
* * * * * * * * * * * * * * * * * * * * * * 28 T1 DS1/ISDN-PRI/J1 framing transceivers All 28 framers are fully independent Frames to D4, ESF, and SLC-96 formats Framing transparent mode Can operate in both loop timing and external timing (common transmit clock) configurations Framing bit clock gapping mode supported Supports H.100 / MVIP 8 MHz interfaces 8-bit parallel control port supports both multiplexed & non-multiplexed buses (Intel or Motorola) Extracts and inserts robbed bit signaling via either software (processor based) or hardware signals Signaling freezing Interrupt generated on change of signaling data Detects and generates yellow (RAI) and blue (AIS) alarms Detects carrier loss (RCL), AIS-CI, and loss of sync (RLOS) Fully independent transmit and receive functionality Generates and detects in-band loop codes from 1 to 8 bits in length including CSU loop codes Contains ANSI one's density monitor and enforcer Large path and line error counters including EXZ, CRC6, and framing bit errors HDLC controller with 64-byte buffers in both transmit and receive paths; configurable for FDL or DS0 access Per-channel code insertion in both transmit and receive paths Ability to monitor one DS0 channel in both the transmit and receive paths 1.544 MHz to 8.192 MHz clock synthesizer Per-channel loopback
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* * * *
Ability to calculate and check CRC6 according to the Japanese standard Ability to pass the F-Bit position through the elastic stores in the H.100 / MVIP 8 MHz backplane mode IEEE 1149.1 support 1.8V & 3.3V supply with 5V tolerant I/O; low power CMOS
Reader's Note: This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125 us frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1. Each channel is made up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used: D4 SLC-96 ESF B8ZS CRC Ft Fs FPS MF BOC HDLC FDL Superframe (12 frames per multiframe) Multiframe Structure Subscriber Loop Carrier - 96 Channels (SLC-96 is an AT&T registered trademark) Extended Superframe (24 frames per multiframe) Multiframe Structure Bipolar with 8 Zero Substitution Cyclical Redundancy Check Terminal Framing Pattern in D4 Signaling Framing Pattern in D4 Framing Pattern in ESF Multiframe Bit Oriented Code High Level Data Link Control Facility Data Link
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DOCUMENT REVISION HISTORY
Revision V1 07-15-99 V2 09-22-99 Notes Initial Release. 1. Added mechanical specifications (Section 22). 2. Added signal/lead assignment (Section 2). 3. Swapped the signal order of the RNRZ12 and VDD_CORE signals (Section 2). 4. Swapped the signal order of the VDD_CORE and TCLK22/RSIG22 signals (Section 2). 5. Removed the TCLK11/RSIG11 signal duplication with TSYNC11/TSIG11 signal (Section 2). 6. Added JTAG boundary scan control bit description (Table 19-2). 7. Added tD2 timing parameter to 8 MHz IBO timing specifications (Figure 21-9). 8. Added special test mode that is invoked via the TEST and FIACT* signals (Section 2). 1. Fixed errors in Table 18-2 (8 MHz IBO Channel Assignment)
V3 02-16-00
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DS3120 28 CHANNEL T1 FRAMER Figure 1-1
28 T1 Framers
Receive Framer Synchronizer Alarm Detection Loop Code Detector CRC/Frame Error Counters One's Density Monitor S/W Signaling Extraction DS0 Channel Marking DS0 Channel Code Insert DS0 Monitor
Receive HDLC & BOM Controller 4
MODE0 to MODE3
RCLK[n]
clock sync data Payload Loopback
clock sync data
RNRZ[n] Remote Loopback Framer Loopback
data
Force High
8Mbps Interleaved Bus Operation (IBO) Buffer
clock sync RSYNC[n] RSER[n]
Hardware Signaling Extraction sync & clock control clock sync 8Mbps Interleaved Bus Operation (IBO) Buffer clock sync Hardware Signaling Insertion
Mode Mux
Transmit Formatter AIS Generation DS0 Monitor One's Density Enforcer Yellow Alarm Generation CRC Generation F-Bit Insertion FDL Insertion Clear Channel Bit 7 Insert S/W Signaling Insertion DS0 Channel Loopback Loop Code Generation DS0 Channel Code Insert DS0 HDLC Insert LOTC mux
clock sync data
TCLK[n] / RSIG[n] TSYNC[n] / TSIG[n] TSER[n]
TNRZ[n]
Force High
Transmit HDLC & BOM Controller 8MSYNC D0 to D7 / AD0 to AD7 INT* MUX A0 to A5, A7 ALE(AS) / A6 RD*(DS*) WR*(R/W*) BTS 7 8MCLKI 8 CTSYNC
1.544MHz to 8.192MHz Synthesizer Parallel Control Port (routed to all blocks) JTAG & Output Control
CTCLK 8MCLKO CLKSI TEST FIACT* JTCLK JTRST* JTMS JTDI JTDO
I/O Supply
FS0 to FS4 CS* 5
8 8
VDD_IO VSS_IO VDD_CORE VSS_CORE
Core Supply
8 8
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TABLE OF CONTENTS
1. INTRODUCTION ................................................................................................................................ 2 2. DS3120 SIGNAL DESCRIPTION....................................................................................................... 8 3. DEVICE OPERATING MODES....................................................................................................... 23 4. DS3120 REGISTER MAP ................................................................................................................. 28 5. PARALLEL PORT............................................................................................................................. 33 6. CONTROL, ID AND TEST REGISTERS......................................................................................... 34 7. STATUS AND INFORMATION REGISTERS ................................................................................ 45 8. ERROR COUNT REGISTERS.......................................................................................................... 54 9. DS0 MONITORING FUNCTION ..................................................................................................... 57 10. SIGNALING OPERATION............................................................................................................ 59
10.1 PROCESSOR BASED SIGNALING.......................................................................................... 60 10.2 HARDWARE BASED SIGNALING.......................................................................................... 61 11. PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK ......................................... 62 11.1 TRANSMIT SIDE CODE GENERATION................................................................................. 63 11.1.1 Simple Idle Code Insertion and Per-Channel Loopback ...................................................... 63 11.1.2 Per-Channel Code Insertion ................................................................................................. 64 11.2 RECEIVE SIDE CODE GENERATION .................................................................................... 65 11.2.1 Simple Code Insertion........................................................................................................... 65 11.2.2 Per-Channel Code Insertion ................................................................................................. 65 12. DS0 SELECT CONTROL REGISTERS........................................................................................ 66 12.1 RCHBLK & TCHBLK USED FOR SIGNALING CONTROL ............................................................. 68 12.2 RCHBLK & TCHBLK USED FOR HDLC CONTROL.................................................................... 68 13. 14. ELASTIC STORE OPERATION ................................................................................................... 68 HDLC CONTROLLER................................................................................................................... 69 GENERAL OVERVIEW.................................................................................................................... 69 STATUS REGISTER FOR THE HDLC ............................................................................................... 70 BASIC OPERATION DETAILS .......................................................................................................... 71 HDLC/BOC REGISTER DESCRIPTION........................................................................................... 72
14.1 14.2 14.3 14.4
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15.
LEGACY FDL SUPPORT & D4/SLC-96 SUPPORT ................................................................... 79 OVERVIEW .................................................................................................................................... 80 RECEIVE SECTION ......................................................................................................................... 80 TRANSMIT SECTION ...................................................................................................................... 81 D4/SLC-96 OPERATION........................................................................................................... 82
15.1 15.2 15.3 15.4 16. 17. 18. 19.
PROGRAMMABLE IN-BAND CODE GENERATION AND DETECTION ............................. 82 TRANSMIT TRANSPARENCY.................................................................................................... 85 8 MHZ INTERLEAVED BUS OPERATION (IBO)...................................................................... 85 JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT ............................ 91 DESCRIPTION ................................................................................................................................ 91 TAP CONTROLLER STATE MACHINE ............................................................................................ 92 INSTRUCTION REGISTER AND INSTRUCTIONS................................................................................. 95 TEST REGISTERS ........................................................................................................................... 96
19.1 19.2 19.3 19.4 20. 21. 22.
TIMING DIAGRAMS .................................................................................................................. 106 OPERATING PARAMETERS..................................................................................................... 110 MECHANICAL PACKAGE SPECIFICATIONS........................................................................ 123
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2. DS3120 SIGNAL DESCRIPTION Signal Description / Lead List (Sorted by Signal Name) Table 2-1
LEAD C11 C12 E11 A8 B8 A7 C8 E8 D8 A6 B7 B11 B12 B5 A12 D11 D10 C10 A9 B9 C9 E10 E9 D9 A3 C7 E7 D7 B6 A4 B10 A2 C5 D5 B4 A1 C2 E4 E3 SIGNAL 8MCLKI 8MCLKO 8MSYNC A0 A1 A2 A3 A4 A5 A6/ALE (AS) A7 BTS CLKSI CS* CTCLK CTSYNC D0 or AD0 D1 or AD1 D2 or AD2 D3 or AD3 D4 or AD4 D5 or AD5 D6 or AD6 D7 or AD7 FIACT* FS0 FS1 FS2 FS3 FS4 INT* JTCLK JTDI JTDO JTMS JTRST* MODE0 MODE1 MODE2 TYPE I O I I I I I I I I I I I I I O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I O (od) I I O I I I I I SIGNAL DESCRIPTION 8 MHz Interleaved Bus Operation (IBO) Clock Input. 8 MHz Clock Synthesizer Output. 8 MHz Interleaved Bus Operation (IBO) Sync Input. Address Bus Bit 0; LSB. Address Bus Bit 1. Address Bus Bit 2. Address Bus Bit 3. Address Bus Bit 4. Address Bus Bit 5. Address Bus Bit 6 / Address Latch Enable (Address Strobe). Address Bus Bit 7; MSB. Bus Type Select for Parallel Control Port 8MCLK Clock Reference Input . Chip Select. Active low. Common Transmit T1 Clock. Common Transmit 8 kHz Frame Sync Pulse. Data Bus Bit or Address/Data Bit 0; LSB. Data Bus Bit or Address/Data Bit 1. Data Bus Bit or Address/Data Bit 2. Data Bus Bit or Address/Data Bit 3. Data Bus Bit or Address/Data Bit 4. Data Bus Bit or Address/Data Bit 5. Data Bus Bit or Address/Data Bit 6. Data Bus Bit or Address/Data Bit 7; MSB. Force Inactive. Active low. Framer Select 0 for Parallel Control Port; LSB. Framer Select 1 for Parallel Control Port. Framer Select 2 for Parallel Control Port. Framer Select 3 for Parallel Control Port. Framer Select 4 for Parallel Control Port; MSB. Receive Alarm Interrupt for all 28 Framers. Active low. JTAG Test Clock. JTAG Test Data Input. JTAG Test Data Output. JTAG Test Mode Select. JTAG Reset. Active low. Mode Select Bit 0. Mode Select Bit 1. Mode Select Bit 2.
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LEAD D2 C6 D3 W3 V4 U4 T5 D18 E16 D17 C18 B3 B2 C4 C3 B1 D4 E5 Y7 T8 Y5 U7 V6 Y3 V5 U3 V2 R4 V1 P4 P3 N5 N3 M5 N1 L4 M1 K5 K1 J5 H2 H5 F1 G4
SIGNAL MODE3 MUX NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 RCLK9 RCLK10 RCLK11 RCLK12 RCLK13 RCLK14 RCLK15 RCLK16 RCLK17 RCLK18 RCLK19 RCLK20 RCLK21 RCLK22 RCLK23 RCLK24 RCLK25 RCLK26
TYPE I I I I I I I I I I I I I I I I I I I I I I I I I I I I
SIGNAL DESCRIPTION Mode Select Bit 3. Non-Multiplexed or Multiplexed Bus Select. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. Receive Clock for Framer 1. Receive Clock for Framer 2. Receive Clock for Framer 3. Receive Clock for Framer 4. Receive Clock for Framer 5. Receive Clock for Framer 6. Receive Clock for Framer 7. Receive Clock for Framer 8. Receive Clock for Framer 9. Receive Clock for Framer 10. Receive Clock for Framer 11. Receive Clock for Framer 12. Receive Clock for Framer 13. Receive Clock for Framer 14. Receive Clock for Framer 15. Receive Clock for Framer 16. Receive Clock for Framer 17. Receive Clock for Framer 18. Receive Clock for Framer 19. Receive Clock for Framer 20. Receive Clock for Framer 21. Receive Clock for Framer 22. Receive Clock for Framer 23. Receive Clock for Framer 24. Receive Clock for Framer 25. Receive Clock for Framer 26.
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LEAD D1 F3 A10 V8 U8 V7 Y4 T7 Y2 U5 T4 T3 Y1 R3 P5 T1 P2 P1 N2 M2 L3 L1 K4 J1 J4 G1 H4 E1 G5 E2 C1 B13 D13 D14 E14 D16 E17 C20 G17 H17 H20 J19 K20 L17
SIGNAL RCLK27 RCLK28 RD*/(DS*) RNRZ1 RNRZ2 RNRZ3 RNRZ4 RNRZ5 RNRZ6 RNRZ7 RNRZ8 RNRZ9 RNRZ10 RNRZ11 RNRZ12 RNRZ13 RNRZ14 RNRZ15 RNRZ16 RNRZ17 RNRZ18 RNRZ19 RNRZ20 RNRZ21 RNRZ22 RNRZ23 RNRZ24 RNRZ25 RNRZ26 RNRZ27 RNRZ28 RSER1 RSER2 RSER3 RSER4 RSER5 RSER6 RSER7 RSER8 RSER9 RSER10 RSER11 RSER12 RSER13
TYPE I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I O O O O O O O O O O O O O
SIGNAL DESCRIPTION Receive Clock for Framer 27. Receive Clock for Framer 28. Read Input (Data Strobe). Active low. Receive NRZ Data for Framer 1. Receive NRZ Data for Framer 2. Receive NRZ Data for Framer 3. Receive NRZ Data for Framer 4. Receive NRZ Data for Framer 5. Receive NRZ Data for Framer 6. Receive NRZ Data for Framer 7. Receive NRZ Data for Framer 8. Receive NRZ Data for Framer 9. Receive NRZ Data for Framer 10. Receive NRZ Data for Framer 11. Receive NRZ Data for Framer 12. Receive NRZ Data for Framer 13. Receive NRZ Data for Framer 14. Receive NRZ Data for Framer 15. Receive NRZ Data for Framer 16. Receive NRZ Data for Framer 17. Receive NRZ Data for Framer 18. Receive NRZ Data for Framer 19. Receive NRZ Data for Framer 20. Receive NRZ Data for Framer 21. Receive NRZ Data for Framer 22. Receive NRZ Data for Framer 23. Receive NRZ Data for Framer 24. Receive NRZ Data for Framer 25. Receive NRZ Data for Framer 26. Receive NRZ Data for Framer 27. Receive NRZ Data for Framer 28. Receive Serial Data from Framer 1. Receive Serial Data from Framer 2. Receive Serial Data from Framer 3. Receive Serial Data from Framer 4. Receive Serial Data from Framer 5. Receive Serial Data from Framer 6. Receive Serial Data from Framer 7. Receive Serial Data from Framer 8. Receive Serial Data from Framer 9. Receive Serial Data from Framer 10. Receive Serial Data from Framer 11. Receive Serial Data from Framer 12. Receive Serial Data from Framer 13.
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LEAD M17 N16 R19 P16 T18 V18 W18 Y19 T14 U13 W13 Y13 W11 U10 T9 A14 A16 B16 A19 B18 E18 F18 G16 H16 J17 J20 L20 M20 N20 N17 P17 R17 T17 T16 V16 Y18 V14 T13 U12 W12 Y11 V10 U9 D12
SIGNAL RSER14 RSER15 RSER16 RSER17 RSER18 RSER19 RSER20 RSER21 RSER22 RSER23 RSER24 RSER25 RSER26 RSER27 RSER28 RSYNC1 RSYNC2 RSYNC3 RSYNC4 RSYNC5 RSYNC6 RSYNC7 RSYNC8 RSYNC9 RSYNC10 RSYNC11 RSYNC12 RSYNC13 RSYNC14 RSYNC15 RSYNC16 RSYNC17 RSYNC18 RSYNC19 RSYNC20 RSYNC21 RSYNC22 RSYNC23 RSYNC24 RSYNC25 RSYNC26 RSYNC27 RSYNC28 TCLK1/RSIG1
TYPE O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O I/O
SIGNAL DESCRIPTION Receive Serial Data from Framer 14. Receive Serial Data from Framer 15. Receive Serial Data from Framer 16. Receive Serial Data from Framer 17. Receive Serial Data from Framer 18. Receive Serial Data from Framer 19. Receive Serial Data from Framer 20. Receive Serial Data from Framer 21. Receive Serial Data from Framer 22. Receive Serial Data from Framer 23. Receive Serial Data from Framer 24. Receive Serial Data from Framer 25. Receive Serial Data from Framer 26. Receive Serial Data from Framer 27. Receive Serial Data from Framer 28. Receive Sync from Framer 1. Receive Sync from Framer 2. Receive Sync from Framer 3. Receive Sync from Framer 4. Receive Sync from Framer 5. Receive Sync from Framer 6. Receive Sync from Framer 7. Receive Sync from Framer 8. Receive Sync from Framer 9. Receive Sync from Framer 10. Receive Sync from Framer 11. Receive Sync from Framer 12. Receive Sync from Framer 13. Receive Sync from Framer 14. Receive Sync from Framer 15. Receive Sync from Framer 16. Receive Sync from Framer 17. Receive Sync from Framer 18. Receive Sync from Framer 19. Receive Sync from Framer 20. Receive Sync from Framer 21. Receive Sync from Framer 22. Receive Sync from Framer 23. Receive Sync from Framer 24. Receive Sync from Framer 25. Receive Sync from Framer 26. Receive Sync from Framer 27. Receive Sync from Framer 28. Transmit Clock / Receive Signaling for/from Framer 1.
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LEAD E13 A17 D15 C16 C19 F17 F19 F20 H19 J18 K19 L16 M16 N18 P18 R18 U19 W19 V17 U15 U14 W14 Y14 V12 V11 T10 V9 D6 W8 Y6 W7 W6 W5 U6 W4 V3 W2 U2 W1 T2 R2 N4 R1 M4
SIGNAL TCLK2/RSIG2 TCLK3/RSIG3 TCLK4/RSIG4 TCLK5/RSIG5 TCLK6/RSIG6 TCLK7/RSIG7 TCLK8/RSIG8 TCLK9/RSIG9 TCLK10/RSIG10 TCLK11/RSIG11 TCLK12/RSIG12 TCLK13/RSIG13 TCLK14/RSIG14 TCLK15/RSIG15 TCLK16/RSIG16 TCLK17/RSIG17 TCLK18/RSIG18 TCLK19/RSIG19 TCLK20/RSIG20 TCLK21/RSIG21 TCLK22/RSIG22 TCLK23/RSIG23 TCLK24/RSIG24 TCLK25/RSIG25 TCLK26/RSIG26 TCLK27/RSIG27 TCLK28/RSIG28 TEST TNRZ1 TNRZ2 TNRZ3 TNRZ4 TNRZ5 TNRZ6 TNRZ7 TNRZ8 TNRZ9 TNRZ10 TNRZ11 TNRZ12 TNRZ13 TNRZ14 TNRZ15 TNRZ16
TYPE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O O O O O O O O O O O O O O O O
SIGNAL DESCRIPTION Transmit Clock / Receive Signaling for/from Framer 2. Transmit Clock / Receive Signaling for/from Framer 3. Transmit Clock / Receive Signaling for/from Framer 4. Transmit Clock / Receive Signaling for/from Framer 5. Transmit Clock / Receive Signaling for/from Framer 6. Transmit Clock / Receive Signaling for/from Framer 7. Transmit Clock / Receive Signaling for/from Framer 8. Transmit Clock / Receive Signaling for/from Framer 9. Transmit Clock / Receive Signaling for/from Framer 10. Transmit Clock / Receive Signaling for/from Framer 11. Transmit Clock / Receive Signaling for/from Framer 12. Transmit Clock / Receive Signaling for/from Framer 13. Transmit Clock / Receive Signaling for/from Framer 14. Transmit Clock / Receive Signaling for/from Framer 15. Transmit Clock / Receive Signaling for/from Framer 16. Transmit Clock / Receive Signaling for/from Framer 17. Transmit Clock / Receive Signaling for/from Framer 18. Transmit Clock / Receive Signaling for/from Framer 19. Transmit Clock / Receive Signaling for/from Framer 20. Transmit Clock / Receive Signaling for/from Framer 21. Transmit Clock / Receive Signaling for/from Framer 22. Transmit Clock / Receive Signaling for/from Framer 23. Transmit Clock / Receive Signaling for/from Framer 24. Transmit Clock / Receive Signaling for/from Framer 25. Transmit Clock / Receive Signaling for/from Framer 26. Transmit Clock / Receive Signaling for/from Framer 27. Transmit Clock / Receive Signaling for/from Framer 28. 3-state Control for all Output and I/O Pins. Transmit NRZ Data from Framer . Transmit NRZ Data from Framer 2. Transmit NRZ Data from Framer 3. Transmit NRZ Data from Framer 4. Transmit NRZ Data from Framer 5. Transmit NRZ Data from Framer 6. Transmit NRZ Data from Framer 7. Transmit NRZ Data from Framer 8. Transmit NRZ Data from Framer 9. Transmit NRZ Data from Framer 10. Transmit NRZ Data from Framer 11. Transmit NRZ Data from Framer 12. Transmit NRZ Data from Framer 13. Transmit NRZ Data from Framer 14. Transmit NRZ Data from Framer 15. Transmit NRZ Data from Framer 16.
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LEAD M3 L5 L2 K2 K3 J2 J3 H3 G2 G3 F2 F4 E12 B14 B15 A18 B17 C17 B20 D20 G19 G20 K16 K17 L18 M18 P20 T20 T19 W20 U18 U16 Y20 W16 Y16 Y15 T11 U11 W10 W9 A13 C13 C14 C15
SIGNAL TNRZ17 TNRZ18 TNRZ19 TNRZ20 TNRZ21 TNRZ22 TNRZ23 TNRZ24 TNRZ25 TNRZ26 TNRZ27 TNRZ28 TSER1 TSER2 TSER3 TSER4 TSER5 TSER6 TSER7 TSER8 TSER9 TSER10 TSER11 TSER12 TSER13 TSER14 TSER15 TSER16 TSER17 TSER18 TSER19 TSER20 TSER21 TSER22 TSER23 TSER24 TSER25 TSER26 TSER27 TSER28 TSYNC1/TSIG1 TSYNC2/TSIG2 TSYNC3/TSIG3 TSYNC4/TSIG4
TYPE O O O O O O O O O O O O I I I I I I I I I I I I I I I I I I I I I I I I I I I I I/O I/O I/O I/O
SIGNAL DESCRIPTION Transmit NRZ Data from Framer 17. Transmit NRZ Data from Framer 18. Transmit NRZ Data from Framer 19. Transmit NRZ Data from Framer 20. Transmit NRZ Data from Framer 21. Transmit NRZ Data from Framer 22. Transmit NRZ Data from Framer 23. Transmit NRZ Data from Framer 24. Transmit NRZ Data from Framer 25. Transmit NRZ Data from Framer 26. Transmit NRZ Data from Framer 27. Transmit NRZ Data from Framer 28. Transmit Serial Data for Framer 1. Transmit Serial Data for Framer 2. Transmit Serial Data for Framer 3. Transmit Serial Data for Framer 4. Transmit Serial Data for Framer 5. Transmit Serial Data for Framer 6. Transmit Serial Data for Framer 7. Transmit Serial Data for Framer 8. Transmit Serial Data for Framer 9. Transmit Serial Data for Framer 10. Transmit Serial Data for Framer 11. Transmit Serial Data for Framer 12. Transmit Serial Data for Framer 13. Transmit Serial Data for Framer 14. Transmit Serial Data for Framer 15. Transmit Serial Data for Framer 16. Transmit Serial Data for Framer 17. Transmit Serial Data for Framer 18. Transmit Serial Data for Framer 19. Transmit Serial Data for Framer 20. Transmit Serial Data for Framer 21. Transmit Serial Data for Framer 22. Transmit Serial Data for Framer 23. Transmit Serial Data for Framer 24. Transmit Serial Data for Framer 25. Transmit Serial Data for Framer 26. Transmit Serial Data for Framer 27. Transmit Serial Data for Framer 28. Transmit Sync / Transmit Signaling for Framer 1. Transmit Sync / Transmit Signaling for Framer 2. Transmit Sync / Transmit Signaling for Framer 3. Transmit Sync / Transmit Signaling for Framer 4.
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LEAD A20 B19 D19 E19 G18 H18 J16 K18 L19 M19 N19 P19 U20 V20 V19 U17 W17 V15 W15 V13 T12 Y12 Y10 Y9 A5 A15 E20 H1 R20 U1 Y17 Y8 E6 E15 F5 F16 J9 J12 M9 M12 R5 R16 T6 T15
SIGNAL TSYNC5/TSIG5 TSYNC6/TSIG6 TSYNC7/TSIG7 TSYNC8/TSIG8 TSYNC9/TSIG9 TSYNC10/TSIG10 TSYNC11/TSIG11 TSYNC12/TSIG12 TSYNC13/TSIG13 TSYNC14/TSIG14 TSYNC15/TSIG15 TSYNC16/TSIG16 TSYNC17/TSIG17 TSYNC18/TSIG18 TSYNC19/TSIG19 TSYNC20/TSIG20 TSYNC21/TSIG21 TSYNC22/TSIG22 TSYNC23/TSIG23 TSYNC24/TSIG24 TSYNC25/TSIG25 TSYNC26/TSIG26 TSYNC27/TSIG27 TSYNC28/TSIG28 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
TYPE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O -
SIGNAL DESCRIPTION Transmit Sync / Transmit Signaling for Framer 5. Transmit Sync / Transmit Signaling for Framer 6. Transmit Sync / Transmit Signaling for Framer 7. Transmit Sync / Transmit Signaling for Framer 8. Transmit Sync / Transmit Signaling for Framer 9. Transmit Sync / Transmit Signaling for Framer 10. Transmit Sync / Transmit Signaling for Framer 11. Transmit Sync / Transmit Signaling for Framer 12. Transmit Sync / Transmit Signaling for Framer 13. Transmit Sync / Transmit Signaling for Framer 14. Transmit Sync / Transmit Signaling for Framer 15. Transmit Sync / Transmit Signaling for Framer 16. Transmit Sync / Transmit Signaling for Framer 17. Transmit Sync / Transmit Signaling for Framer 18. Transmit Sync / Transmit Signaling for Framer 19. Transmit Sync / Transmit Signaling for Framer 20. Transmit Sync / Transmit Signaling for Framer 21. Transmit Sync / Transmit Signaling for Framer 22. Transmit Sync / Transmit Signaling for Framer 23. Transmit Sync / Transmit Signaling for Framer 24. Transmit Sync / Transmit Signaling for Framer 25. Transmit Sync / Transmit Signaling for Framer 26. Transmit Sync / Transmit Signaling for Framer 27. Transmit Sync / Transmit Signaling for Framer 28. Positive Supply Voltage for the Core Logic. Positive Supply Voltage for the Core Logic. Positive Supply Voltage for the Core Logic. Positive Supply Voltage for the Core Logic. Positive Supply Voltage for the Core Logic. Positive Supply Voltage for the Core Logic. Positive Supply Voltage for the Core Logic. Positive Supply Voltage for the Core Logic. Positive Supply Voltage for the Input & Output Buffers. Positive Supply Voltage for the Input & Output Buffers. Positive Supply Voltage for the Input & Output Buffers. Positive Supply Voltage for the Input & Output Buffers. Positive Supply Voltage for the Input & Output Buffers. Positive Supply Voltage for the Input & Output Buffers. Positive Supply Voltage for the Input & Output Buffers. Positive Supply Voltage for the Input & Output Buffers. Positive Supply Voltage for the Input & Output Buffers. Positive Supply Voltage for the Input & Output Buffers. Positive Supply Voltage for the Input & Output Buffers. Positive Supply Voltage for the Input & Output Buffers.
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LEAD J10 J11 K9 K10 K11 K12 L9 L10 L11 L12 M10 M11 A11
SIGNAL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS WR*/(R/W*)
TYPE I
SIGNAL DESCRIPTION Signal Ground for the Input & Output Buffers & the Core. Signal Ground for the Input & Output Buffers & the Core. Signal Ground for the Input & Output Buffers & the Core. Signal Ground for the Input & Output Buffers & the Core. Signal Ground for the Input & Output Buffers & the Core. Signal Ground for the Input & Output Buffers & the Core. Signal Ground for the Input & Output Buffers & the Core. Signal Ground for the Input & Output Buffers & the Core. Signal Ground for the Input & Output Buffers & the Core. Signal Ground for the Input & Output Buffers & the Core. Signal Ground for the Input & Output Buffers & the Core. Signal Ground for the Input & Output Buffers & the Core. Write Input (Read/Write). Active low.
TRANSMIT SIDE SIGNALS
Signal Name: Signal Description: Signal Type: Mode 1 TCLK1 to TCLK28 / RSIG1 to RSIG28 Transmit Clock / Receive Signaling Output Input/Output / Output Function of TCLK/RSIG Signal Outputs a T1 clock which is based on the receive clock (RCLK) from the associated receive side framer. Outputs a T1 clock which is based on the receive clock (RCLK) from the associated receive side framer. Outputs a T1 clock which is based on the clock applied at CTCLK. Outputs a T1 clock which is based on the clock applied at CTCLK. Outputs receive side signaling bits in a PCM format. Updated on the rising edge of RCLK. Outputs receive side signaling bits in a PCM format. Updated on the rising edge of RCLK. Outputs receive side signaling bits in a PCM format. Updated on the rising edge of RCLK. Outputs receive side signaling bits in a PCM format. Updated on the rising edge of RCLK. Outputs receive side signaling bits in a PCM format. Updated on the rising edge of 8MCLKI. Outputs receive side signaling bits in a PCM format. Updated on the rising edge of 8MCLKI.
2 3
4
5 6 7 8 9 10
Mode Description Normal Loop Timed with no Gapped Clocks on RSYNC & TSYNC Normal Loop Timed with Gapped Clocks on RSYNC & TSYNC Normal External Timed with no Gapped Clocks on RSYNC & TSYNC Normal External Timed with Gapped Clocks on RSYNC & TSYNC RSIG/TSIG Access Loop Timed with no Gapped Clocks on RSYNC RSIG/TSIG Access Loop Timed with Gapped Clocks on RSYNC RSIG/TSIG Access External Timed with no Gapped Clocks on RSYNC RSIG/TSIG Access External Timed with Gapped Clocks on RSYNC 8 Mbps IBO Loop Timed 8 Mbps IBO External Timed
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Mode 11
12
13
Mode Description Independent TCLK Timing with TSYNC an Input and no Gapped Clocks on RSYNC & TSYNC Independent TCLK Timing with TSYNC an Output and no Gapped Clocks on RSYNC & TSYNC Independent TCLK Timing with TSYNC an Output and Gapped Clocks on RSYNC & TSYNC
Function of TCLK/RSIG Signal Inputs an independent T1 clock for each of the 28 formatters. Inputs an independent T1 clock for each of the 28 formatters. Inputs an independent T1 clock for each of the 28 formatters.
Signal Name: CTCLK Signal Description: Common Transmit Clock Signal Type: Input Transmit T1 (1.544 MHz) clock that can be used for all 28 transmit formatters. Signal Name: CTSYNC Signal Description: Common Transmit Frame Sync Signal Type: Output An output that pulses high for one CTCLK or 8MCLKI during the F-bit position to indicate the transmit 8 kHz frame boundary. Signal Name: Signal Description: Signal Type: Mode 1 TSYNC1 to TSYNC28 / TSIG1 to TSIG28 Transmit Sync / Transmit Signaling Input Input/Output / Input Function of TSYNC/TSIG Signal Outputs a one TCLK wide 8 kHz frame sync pulse.
2 3
4
5 6 7 8
Mode Description Normal Loop Timed with no Gapped Clocks on RSYNC & TSYNC Normal Loop Timed with Gapped Clocks on RSYNC & TSYNC Normal External Timed with no Gapped Clocks on RSYNC & TSYNC Normal External Timed with Gapped Clocks on RSYNC & TSYNC RSIG/TSIG Access Loop Timed with no Gapped Clocks on RSYNC RSIG/TSIG Access Loop Timed with Gapped Clocks on RSYNC RSIG/TSIG Access External Timed with no Gapped Clocks on RSYNC RSIG/TSIG Access External Timed with Gapped Clocks on RSYNC
Outputs a gapped T1 clock which suppresses a clock pulse during the F-Bit position. Outputs a one TCLK wide 8 kHz frame sync pulse.
Outputs a gapped T1 clock which suppresses a clock pulse during the F-Bit position. Inputs transmit side signaling bits in a PCM format. Sampled on the falling edge of RCLK. Inputs transmit side signaling bits in a PCM format. Sampled on the falling edge of RCLK. Inputs transmit side signaling bits in a PCM format. Sampled on the falling edge of CTCLK. Inputs transmit side signaling bits in a PCM format. Sampled on the falling edge of CTCLK.
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Mode 9 10 11
Mode Description 8 Mbps IBO Loop Timed 8 Mbps IBO External Timed Independent TCLK Timing with TSYNC an Input and no Gapped Clocks on RSYNC & TSYNC Independent TCLK Timing with TSYNC an Output and no Gapped Clocks on RSYNC & TSYNC Independent TCLK Timing with TSYNC an Output and Gapped Clocks on RSYNC & TSYNC
12
Function of TSYNC/TSIG Signal Inputs transmit side signaling bits in a PCM format. Sampled on the falling edge of 8MCLKI. Inputs transmit side signaling bits in a PCM format. Sampled on the falling edge of 8MCLKI. Inputs a 8 kHz frame sync pulse which establishes the frame boundaries independently for each of the 28 formatters. Outputs a one TCLK wide 8 kHz frame sync pulse.
13
Outputs a gapped T1 clock which suppresses a clock pulse during the F-Bit position.
Signal Name: TNRZ1 to TNRZ28 Signal Description: Transmit NRZ Data Output Signal Type: Output Updated on the rising edge of TCLK or CTCLK with the NRZ data out of the transmit side formatter. Signal Name: TSER1 to TSER28 Signal Description: Transmit Serial Data Signal Type: Input Transmit NRZ serial data. Sampled on the falling edge of TCLK, CTCLK or 8MCLKI.
RECEIVE SIDE SIGNALS
Signal Name: RNRZ1 to RNRZ28 Signal Description: Receive NRZ Data Input Signal Type: Input Sampled on the falling edge of RCLK for data to be clocked through the receive side framer. Signal Name: RCLK1 to RCLK28 Signal Description: Receive Clock Input Signal Type: Input T1 input clock used to clock data through the receive side framer. Signal Name: RSER1 to RSER28 Signal Description: Receive Serial Data Signal Type: Output Received NRZ serial data. Updated on the rising edge of RCLK or 8MCLKI.
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Signal Name: RSYNC1 to RSYNC28 Signal Description: Receive Sync Signal Type: Output In Modes 1, 3, 5, 7, 9, 10, 11, & 12, RSYNC provides an extracted 8 kHz pulse, one RCLK wide which identifies frame boundaries. In Modes 2, 4, 6, 8, and 13, RSYNC provides a "gapped" RCLK which has the clock pulse during the F-Bit position suppressed. See Section 20 for timing details.
8 MHZ SIGNALS
Signal Name: CLKSI Signal Description: 8 MHz Clock Reference Signal Type: Input A 1.544 MHz reference clock used in the generation of 8MCLK. Signal Name: 8MCLK Signal Description: 8 MHz Clock Signal Type: Output A 8.192 MHz output clock that is referenced to the T1 clock that is input at the CLKSI signal. Signal Name: 8MCLKI Signal Description: 8 MHz IBO Clock Signal Type: Input A 8.192 MHz clock used in Modes 9 & 10 to support Interleaved Bus Operation (IBO). Should be tied low in modes other than 9 & 10. Signal Name: 8MSYNC Signal Description: 8 kHz Frame Sync for the 8 MHz IBO Mode Signal Type: Input A 8 kHz frame sync that is referenced to the 8MCLKI signal to indicate frame boundaries; supports Interleaved Bus Operation (IBO) in Modes 9 & 10. Should be tied low in modes other than 9 & 10.
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MODE SELECT SIGNALS
Signal Name: MODE0 to MODE3 Signal Description: Device Operating Mode Select Signal Type: Input MODE0 to MODE3 select the operating mode for the device. The device should be reset when changing device modes. MODE3/MODE2/MODE1/MODE0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Mode 1 2 3 4 5 6 7 8 9 10 11 12 13 Mode Description Normal Loop Timed with no Gapped Clocks on RSYNC & TSYNC Normal Loop Timed with Gapped Clocks on RSYNC & TSYNC Normal External Timed with no Gapped Clocks on RSYNC & TSYNC Normal External Timed with Gapped Clocks on RSYNC & TSYNC RSIG/TSIG Access Loop Timed with no Gapped Clocks on RSYNC RSIG/TSIG Access Loop Timed with Gapped Clocks on RSYNC RSIG/TSIG Access External Timed with no Gapped Clocks on RSYNC RSIG/TSIG Access External Timed with Gapped Clocks on RSYNC 8 Mbps IBO Loop Timed 8 Mbps IBO External Timed Independent TCLK Timing with TSYNC an Input and no Gapped Clocks on RSYNC & TSYNC Independent TCLK Timing with TSYNC an Output and no Gapped Clocks on RSYNC & TSYNC Independent TCLK Timing with TSYNC an Output and Gapped Clocks on RSYNC & TSYNC Reserved Reserved Reserved
PARALLEL CONTROL PORT SIGNALS
Signal Name: INT* Signal Description: Interrupt Signal Type: Output (open drain) Flags host controller during important change of conditions in device status. Active low, open drain output.
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Signal Name: MUX Signal Description: Bus Operation Signal Type: Input Set low to select non-multiplexed bus operation. Set high to select multiplexed bus operation. Signal Name: D0 to D7 / AD0 to AD7 Signal Description: Data Bus / Address/Data Bus Signal Type: Input /Output In non-multiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation (MUX = 1), serves as a 8-bit multiplexed address / data bus. Signal Name: A0 to A5, A7 Signal Description: Address Bus Signal Type: Input In non-multiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation (MUX = 1), these pins are not used and should be tied low. Signal Name: ALE(AS) / A6 Signal Description: A6 or Address Latch Enable (Address Strobe) Signal Type: Input In non-multiplexed bus operation (MUX = 0), serves as address bit 6. In multiplexed bus operation (MUX = 1), serves to demultiplex the bus on a positive-going edge. Signal Name: BTS Signal Description: Bus Type Select Signal Type: Input Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD*(DS*), ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the function listed in parenthesis (). Signal Name: RD*(DS*) Signal Description: Read Input (Data Strobe) Signal Type: Input RD* and DS* are active low signals. Refer to bus timing diagrams in Section 21. Signal Name: CS* Signal Description: Chip Select Signal Type: Input Must be low to read or write to the device. CS* is an active low signal. Signal Name: WR*( R/W*) Signal Description: Write Input(Read/Write) Signal Type: Input WR* is an active low signal.
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Signal Name: FS0 to FS4 Signal Description: Framer Selects Signal Type: Input Selects which of the 28 framers to be accessed. FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Framer Accessed 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FS4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Framer Accessed 17 18 19 20 21 22 23 24 25 26 27 28 reserved reserved reserved ISR1/2/3/4
Note:
The ISR1/2/3/4 registers are accessed when FS0 to FS4 is set to 11111.
TEST ACCESS PORT SIGNALS
Signal Name: TEST Signal Description: 3-State Control Signal Type: Input Set high to 3-state all output and I/O pins (including the parallel control port) when JTRST* is tied low. Set low for normal operation. Ignored when JTRST* = 1. Useful in board level testing. Note: TEST should not be tied high when FIACT* is active (i.e., FIACT* = 0) as this will place the device into a special test mode. Signal Name: FIACT* Signal Description: Force RSER, TNRZ, and INT* Inactive Signal Type: Input Set low for force INT* high (i.e., open drain) and RSER1 to RSER28 and TNRZ1 to TNRZ28 high. Set high for normal operation. Ignored when JTRST* = 1 or TEST = 1. Useful for placing the major outputs of the device into a known state on power-up. Note: FIACT* should not be tied low when TEST is active (i.e., TEST = 1) as this will place the device into a special test mode.
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Signal Name: JTRST* Signal Description: IEEE 1149.1 Test Reset Signal Type: Input This signal is used to asynchronously reset the test access port controller. At power up, JTRST* must be set low and then high. This action will set the device into the DEVICE ID mode allowing normal device operation. If boundary scan is not used, this pin should be tied to ground. This pin is pulled up internally by a 10K ohm resistor. Signal Name: JTMS Signal Description: IEEE 1149.1 Test Mode Select Signal Type: Input This pin is sampled on the rising edge of JTCLK and is used to place the test port into the various defined IEEE 1149.1 states. This pin is pulled up internally by a 10K ohm resistor. If not used, this pin should be left unconnected. Signal Name: JTCLK Signal Description: IEEE 1149.1 Test Clock Signal Signal Type: Input This signal is used to shift data into JTDI pin on the rising edge and out of JTDO pin on the falling edge. If not used, this pin should be connected to ground. Signal Name: JTDI Signal Description: IEEE 1149.1 Test Data Input Signal Type: Input Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin is pulled up internally by a 10K ohm resistor. If not used, this pin should be left unconnected. Signal Name: JTDO Signal Description: IEEE 1149.1 Test Data Output Signal Type: Output Test instructions and data are clocked out of this pin on the falling edge of JTCLK.
SUPPLY SIGNALS
Signal Name: Signal Description: Signal Type: 1.8 ( 5%) volts. Signal Name: Signal Description: Signal Type: 3.3 ( 10%) volts. VDD_CORE Positive Supply for the Core Logic Supply
VDD_IO Positive Supply for the Input & Output Buffers Supply
Signal Name: VSS Signal Description: Signal Ground for the Input & Output Buffers and the Core Logic Signal Type: Supply 0.0 volts. All VSS signals should be tied together.
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3. DEVICE OPERATING MODES
The DS3120 can be operated in one of 13 different modes. The operating mode of the device is selected via the MODE0 to MODE3 signals. See Table 13-1. The various operating modes of the device can be broken down into one of four major configurations: Normal Standard configuration with data and frame syncs output on the receive side. On the transmit side, clock and frame sync are output and data is sampled Robbed bit signaling is accessible via the RSIG and TSIG signals; RSIG is made available at the expense of the transmit clock output and TSIG is made available at the expense of the transmit frame sync output Backplane option that aggregates four T1 data streams into a single 8.192 MHz data stream; see Section 18 for a more detailed explanation of this mode Allows each transmit framer to be clocked independently
Hardware Based Signaling 8 MHz IBO (supports H.100 & MVIP applications) Independent TCLK
Each of the configurations above can be set up as either "Loop Timed" or External Timed" as described below. Loop Timed External Timed The clock and frame sync from each receive side framer is routed back to the respective transmit side formatter The transmit side clock and frame sync are generated from a common externally supplied T1 clock source
Also each configuration allows the RSYNC, TSYNC and CTSYNC frame sync signals to supply either a 8 kHz frame sync pulse or a gapped clock. No Gapped Clocks Gapped Clocks The sync signals supply a one clock wide 8 kHz frame sync pulse The sync signals supply a T1 clock that is gapped (i.e., the clock pulse is suppressed) during the F bit position
DS3120 Mode Selection Table 13-1
MODE3/MODE2/MODE1/MODE0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 Mode 1 2 3 4 5 6 7 Mode Description Normal Loop Timed with no Gapped Clocks on RSYNC & TSYNC Normal Loop Timed with Gapped Clocks on RSYNC & TSYNC Normal External Timed with no Gapped Clocks on RSYNC & TSYNC Normal External Timed with Gapped Clocks on RSYNC & TSYNC RSIG/TSIG Access Loop Timed with no Gapped Clocks on RSYNC RSIG/TSIG Access Loop Timed with Gapped Clocks on RSYNC RSIG/TSIG Access External Timed with no Gapped
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MODE3/MODE2/MODE1/MODE0 0 1 1 1 1 1 1 1 1 Mode 1 Mode 2 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1
Mode 8 9 10 11 12 13 -
Mode Description Clocks on RSYNC RSIG/TSIG Access External Timed with Gapped Clocks on RSYNC 8 Mbps IBO Loop Timed 8 Mbps IBO External Timed Independent TCLK Timing with TSYNC an Input and no Gapped Clocks on RSYNC & TSYNC Independent TCLK Timing with TSYNC an Output and no Gapped Clocks on RSYNC & TSYNC Independent TCLK Timing with TSYNC an Output and Gapped Clocks on RSYNC & TSYNC Reserved Reserved Reserved
Normal Loop Timed with no Gapped Clocks on RSYNC & TSYNC Normal Loop Timed with Gapped Clocks on RSYNC & TSYNC
Modes 1 and 2 Figure 3-1
RCLK RNRZ Receive Framer 1 clock sync data clock sync data clock sync data clock sync data RSYNC RSER TCLK TSYNC TSER RSYNC RSER TCLK TSYNC TSER
TNRZ RCLK RNRZ
Transmit Formatter 1
Receive Framer 2
TNRZ
Transmit Formatter 2
RCLK RNRZ Receive Framer 28
TNRZ
Transmit Formatter 28 8kHz Frame Sync Generation 8kHz Frame Sync Generation
clock sync data clock sync data
RSYNC RSER TCLK TSYNC TSER 8MCLKI 8MSYNC CTCLK CTSYNC
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Mode 3 Mode 4
Normal External Timed with no Gapped Clocks on RSYNC & TSYNC Normal External Timed with Gapped Clocks on RSYNC & TSYNC
Modes 3 and 4 Figure 3-2
RCLK RNRZ Receive Framer 1 sync data clock sync data sync data clock sync data RSYNC RSER TCLK TSYNC TSER RSYNC RSER TCLK TSYNC TSER
TNRZ RCLK RNRZ
Transmit Formatter 1
Receive Framer 2
TNRZ
Transmit Formatter 2
RCLK RNRZ Receive Framer 28 sync data clock sync data RSYNC RSER TCLK TSYNC TSER 8MCLKI 8MSYNC CTCLK CTSYNC
TNRZ
Transmit Formatter 28 8kHz Frame Sync Generation 8kHz Frame Sync Generation
Mode 5 Mode 6
RSIG/TSIG Access Loop Timed with no Gapped Clocks on RSYNC RSIG/TSIG Access Loop Timed with Gapped Clocks on RSYNC
Modes 5 and 6 Figure 3-3
RCLK RNRZ Receive Framer 1 clock sync data clock sync data clock sync data clock sync data RSYNC RSER & RSIG
TNRZ RCLK RNRZ
Transmit Formatter 1
TSER & TSIG RSYNC RSER & RSIG
Receive Framer 2
TNRZ
Transmit Formatter 2
TSER & TSIG
RCLK RNRZ Receive Framer 28
TNRZ
Transmit Formatter 28 8kHz Frame Sync Generation 8kHz Frame Sync Generation
clock sync data clock sync data
RSYNC RSER & RSIG
TSER & TSIG 8MCLKI 8MSYNC CTCLK CTSYNC
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Mode 7 Mode 8
RSIG/TSIG Access External Timed with no Gapped Clocks on RSYNC RSIG/TSIG Access External Timed with Gapped Clocks on RSYNC
Modes 7 and 8 Figure 3-4
RCLK RNRZ Receive Framer 1 sync data clock sync data sync data clock sync data RSYNC RSER & RSIG
TNRZ RCLK RNRZ
Transmit Formatter 1
TSER & TSIG RSYNC RSER & RSIG
Receive Framer 2
TNRZ
Transmit Formatter 2
TSER & TSIG
RCLK RNRZ Receive Framer 28 sync data clock sync data RSYNC RSER & RSIG
TNRZ
Transmit Formatter 28 8kHz Frame Sync Generation 8kHz Frame Sync Generation
TSER & TSIG 8MCLKI 8MSYNC CTCLK CTSYNC
Mode 9
8 Mbps IBO Loop Timed
Mode 9 Figure 3-5
RCLK RNRZ Receive Framer 1 clock sync data clock sync data clock sync data clock sync data IBO Buffer IBO Buffer IBO Buffer IBO Buffer
RSER & RSIG
TNRZ RCLK RNRZ
Transmit Formatter 1
TSER & TSIG
Receive Framer 2
RSER & RSIG
TNRZ
Transmit Formatter 2
TSER & TSIG
RCLK RNRZ Receive Framer 28
TNRZ
Transmit Formatter 28 8kHz Frame Sync Generation 8kHz Frame Sync Generation
clock sync data clock sync data
IBO Buffer IBO Buffer
RSER & RSIG
TSER & TSIG 8MCLKI 8MSYNC CTCLK CTSYNC
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Mode 10
8 Mbps IBO External Timed
Mode 10 Figure 3-6
RCLK RNRZ Receive Framer 1 clock sync data clock sync data clock sync data clock sync data IBO Buffer IBO Buffer IBO Buffer IBO Buffer
RSER & RSIG
TNRZ RCLK RNRZ
Transmit Formatter 1
TSER & TSIG
Receive Framer 2
RSER & RSIG
TNRZ
Transmit Formatter 2
TSER & TSIG
RCLK RNRZ Receive Framer 28
TNRZ
Transmit Formatter 28 8kHz Frame Sync Generation 8kHz Frame Sync Generation
clock sync data clock sync data
IBO Buffer IBO Buffer
RSER & RSIG
TSER & TSIG 8MCLKI 8MSYNC CTCLK CTSYNC
Mode 11
Independent TCLK Timing with TSYNC an Input and no Gapped Clocks on RSYNC & TSYNC
Mode 11 Figure 3-7
RCLK RNRZ Receive Framer 1 sync data clock sync data sync data clock sync data RSYNC RSER TCLK TSYNC TSER RSYNC RSER TCLK TSYNC TSER
TNRZ RCLK RNRZ
Transmit Formatter 1
Receive Framer 2
TNRZ
Transmit Formatter 2
RCLK RNRZ Receive Framer 28 sync data clock sync data RSYNC RSER TCLK TSYNC TSER 8MCLKI 8MSYNC CTCLK CTSYNC
TNRZ
Transmit Formatter 28 8kHz Frame Sync Generation 8kHz Frame Sync Generation
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Mode 12 Mode 13
Independent TCLK Timing with TSYNC an Output and no Gapped Clocks on RSYNC & TSYNC Independent TCLK Timing with TSYNC an Output and Gapped Clocks on RSYNC & TSYNC
Modes 12 and 13 Figure 3-8
RCLK RNRZ Receive Framer 1 sync data clock sync data sync data clock sync data RSYNC RSER TCLK TSYNC TSER RSYNC RSER TCLK TSYNC TSER
TNRZ RCLK RNRZ
Transmit Formatter 1
Receive Framer 2
TNRZ
Transmit Formatter 2
RCLK RNRZ Receive Framer 28 sync data clock sync data RSYNC RSER TCLK TSYNC TSER 8MCLKI 8MSYNC CTCLK CTSYNC
TNRZ
Transmit Formatter 28 8kHz Frame Sync Generation 8kHz Frame Sync Generation
4. DS3120 REGISTER MAP Register Map Sorted by Address Table 4-1
ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 R/W R/W R/W R/W R/W R/W R R/W R/W W - R/W - - - - R R/W R/W REGISTER NAME HDLC Control HDLC Status HDLC Interrupt Mask Receive HDLC Information Receive Bit Oriented Code Receive HDLC FIFO Transmit HDLC Information Transmit Bit Oriented Code Transmit HDLC FIFO Not used Common Control 7 Not used Not used Not used Not used Device ID Receive Information 3 Common Control 4
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REGISTER ABBREVIATION HCR HSR HIMR RHIR RBOC RHFR THIR TBOC THFR (set to 00h) CCR7 (set to 00h) (set to 00h) (set to 00h) (set to 00h) IDR RIR3 CCR4
DS3120
ADDRESS 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D
R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
REGISTER NAME In-Band Code Control Transmit Code Definition Receive Up Code Definition Receive Down Code Definition Transmit Channel Control 1 Transmit Channel Control 2 Transmit Channel Control 3 Common Control 5 Transmit DS0 Monitor Receive Channel Control 1 Receive Channel Control 2 Receive Channel Control 3 Common Control 6 Receive DS0 Monitor Status 1 Status 2 Receive Information 1 Line Code Violation Count 1 Line Code Violation Count 2 Path Code Violation Count 1 Path Code violation Count 2 Multiframe Out of Sync Count 2 Receive FDL Register Receive FDL Match 1 Receive FDL Match 2 Receive Control 1 Receive Control 2 Receive Mark 1 Receive Mark 2 Receive Mark 3 Common Control 3 Receive Information 2 Transmit Channel Blocking 1 Transmit Channel blocking 2 Transmit Channel Blocking 3 Transmit Control 1 Transmit Control 2 Common Control 1 Common Control 2 Transmit Transparency 1 Transmit Transparency 2 Transmit Transparency 3 Transmit Idle 1 Transmit Idle 2
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REGISTER ABBREVIATION IBCC TCD RUPCD RDNCD TCC1 TCC2 TCC3 CCR5 TDS0M RCC1 RCC2 RCC3 CCR6 RDS0M SR1 SR2 RIR1 LCVCR1 CVCR2 PCVCR1 PCVCR2 MOSCR2 RFDL RMTCH1 RMTCH2 RCR1 RCR2 RMR1 RMR2 RMR3 CCR3 RIR2 TCBR1 TCBR2 TCBR3 TCR1 TCR2 CCR1 CCR2 TTR1 TTR2 TTR3 TIR1 TIR2
DS3120
ADDRESS 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R
REGISTER NAME Transmit Idle 3 Transmit Idle Definition Transmit Channel 9 Transmit Channel 10 Transmit Channel 11 Transmit Channel 12 Transmit Channel 13 Transmit Channel 14 Transmit Channel 15 Transmit Channel 16 Transmit Channel 17 Transmit Channel 18 Transmit Channel 19 Transmit Channel 20 Transmit Channel 21 Transmit Channel 22 Transmit Channel 23 Transmit Channel 24 Transmit Channel 1 Transmit Channel 2 Transmit Channel 3 Transmit Channel 4 Transmit Channel 5 Transmit Channel 6 Transmit Channel 7 Transmit Channel 8 Receive Channel 17 Receive Channel 18 Receive Channel 19 Receive Channel 20 Receive Channel 21 Receive Channel 22 Receive Channel 23 Receive Channel 24 Receive Signaling 1 Receive Signaling 2 Receive Signaling 3 Receive Signaling 4 Receive Signaling 5 Receive Signaling 6 Receive Signaling 7 Receive Signaling 8 Receive Signaling 9 Receive Signaling 10
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REGISTER ABBREVIATION TIR3 TIDR TC9 TC10 TC11 TC12 TC13 TC14 TC15 TC16 TC17 TC18 TC19 TC20 TC21 TC22 TC23 TC24 TC1 TC2 TC3 TC4 TC5 TC6 TC7 TC8 RC17 RC18 RC19 RC20 RC21 RC22 RC23 RC24 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10
DS3120
ADDRESS 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95
R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -
REGISTER NAME Receive Signaling 11 Receive Signaling 12 Receive Channel Blocking 1 Receive Channel Blocking 2 Receive Channel Blocking 3 Interrupt Mask 2 Transmit Signaling 1 Transmit Signaling 2 Transmit Signaling 3 Transmit Signaling 4 Transmit Signaling 5 Transmit Signaling 6 Transmit Signaling 7 Transmit Signaling 8 Transmit Signaling 9 Transmit Signaling 10 Transmit Signaling 11 Transmit Signaling 12 Not used Test 1 Transmit FDL Register Interrupt Mask Register 1 Receive Channel 1 Receive Channel 2 Receive Channel 3 Receive Channel 4 Receive Channel 5 Receive Channel 6 Receive Channel 7 Receive Channel 8 Receive Channel 9 Receive Channel 10 Receive Channel 11 Receive Channel 12 Receive Channel 13 Receive Channel 14 Receive Channel 15 Receive Channel 16 Receive HDLC DS0 Control Register 1 Receive HDLC DS0 Control Register 2 Transmit HDLC DS0 Control Register 1 Transmit HDLC DS0 Control Register 2 Interleave Bus Operation Register Not used
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REGISTER ABBREVIATION RS11 RS12 RCBR1 RCBR2 RCBR3 IMR2 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 (set to 00h) TEST1 (set to 00h) TFDL IMR1 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 RC10 RC11 RC12 RC13 RC14 RC15 RC16 RDC1 RDC2 TDC1 TDC2 IBO (set to 00h)
DS3120
ADDRESS 96 97 98 99 9A 9B 9C 9D 9E 9F
R/W R/W - - - - - - - - - Test 2 Not used Not used Not used Not used Not used Not used Not used Not used Not used
REGISTER NAME
REGISTER ABBREVIATION TEST2 (set to 00h) (set to 00h) (set to 00h) (set to 00h) (set to 00h) (set to 00h) (set to 00h) (set to 00h) (set to 00h) (set to 00h)
NOTES:
1. Test Registers 1 and 2 are used only by the factory; these registers must be cleared (set to all zeros) on power- up initialization to insure proper operation. 2. Register banks AxH, BxH, CxH, DxH, ExH, and FxH are not accessible.
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DS3120
5. PARALLEL PORT
The DS3120 is controlled via either a non-multiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The DS3120 can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parenthesis (). The external microcontroller will determine which framer is to be accessed via the setting of the FS0 to FS4 signals. See Table 5-1. See the timing diagrams in the A.C. Electrical Characteristics in Section 21 for more details.
Framer Select Decode Table 5-1
FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Framer Accessed 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FS4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Framer Accessed 17 18 19 20 21 22 23 24 25 26 27 28 reserved reserved reserved ISR1/2/3/4
Note:
The ISR1/2/3/4 registers are accessed when FS0 to FS4 is set to 11111.
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DS3120
6. CONTROL, ID AND TEST REGISTERS
The operation of each framer within the DS3120 is configured via a set of eleven control registers. Typically, the control registers are only accessed when the system is first powered up. Once a channel in the DS3120 has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. There are two Receive Control Register (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2), and seven Common Control Registers (CCR1 to CCR7). Each of the eleven registers are described in this section. There is a device Identification Register (IDR) at address 0Fh.
Power-Up Sequence
The DS3120 does not automatically clear its register space on power-up. After the supplies are stable, each of the 28 framer's register space should be configured for operation by writing to all of the internal registers. This includes setting the Test and all unused registers to 00 Hex. This can be accomplished using a two-pass approach on each framer within the DS3120. 1. Clear each framer's register space by writing 00h to the addresses 00h through 09Fh. 2. Program required registers to achieve desired operating mode.
IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)
(MSB) T1E1 SYMBOL T1E1 0 0 POSITION IDR.7 0 ID3 ID2 ID1 (LSB) ID0
NAME AND DESCRIPTION T1 or E1 Chip Determination Bit. 0=T1 chip 1=E1 chip Chip Revision Bit 3. MSB of a decimal code that represents the chip revision. Chip Revision Bit 2. Chip Revision Bit 1. Chip Revision Bit 0. LSB of a decimal code that represents the chip revision.
ID3 ID2 ID1 ID0
IDR.3 IDR.1 IDR.2 IDR.0
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DS3120
RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex)
(MSB) 1 SYMBOL 1 ARC ARC OOF1 POSITION RCR1.7 RCR1.6 OOF2 SYNCC SYNCT SYNCE (LSB) RESYNC
NAME AND DESCRIPTION This control bit must be set to one. Auto Resync Criteria. 0 = Resync on OOF or RCL event 1 = Resync on OOF only Out Of Frame Select 1. 0 = 2/4 frame bits in error 1 = 2/5 frame bits in error Out Of Frame Select 2. 0 = follow RCR1.5 1 = 2/6 frame bits in error Sync Criteria. In D4 Framing Mode. 0 = search for Ft pattern, then search for Fs pattern 1 = cross couple Ft and Fs pattern In ESF Framing Mode. 0 = search for FPS pattern only 1 = search for FPS and verify with CRC6 Sync Time. 0 = qualify 10 bits 1 = qualify 24 bits Sync Enable. 0 = auto resync enabled 1 = auto resync disabled Resync. When toggled from low to high, a resynchronization of the receive side framer is initiated. Must be cleared and set again for a subsequent resync.
OOF1
RCR1.5
OOF2
RCR1.4
SYNCC
RCR1.3
SYNCT
RCR1.2
SYNCE
RCR1.1
RESYNC
RCR1.0
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DS3120
RCR2: RECEIVE CONTROL REGISTER 2 (Address=2C Hex)
(MSB) RCS SYMBOL RCS 0 0 POSITION RCR2.7 0 1 RD4YM FSBE (LSB) MOSCRF
NAME AND DESCRIPTION Receive Code Select. See Section 11 for more details. 0 = idle code (7F Hex) 1 = digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex) This control bit must be set to zero. This control bit must be set to zero. This control bit must be set to zero. This control bit must be set to one. Receive Side D4 Yellow Alarm Select. 0 = zeros in bit 2 of all channels 1 = a one in the S-bit position of frame 12 PCVCR Fs-Bit Error Report Enable. 0 = do not report bit errors in Fs-bit position; only Ft bit position 1 = report bit errors in Fs-bit position as well as Ft bit position Multiframe Out of Sync Count Register Function Select. 0 = count errors in the framing bit position 1 = count the number of multiframes out of sync
0 0 0 1 RD4YM
RCR2.6 RCR2.5 RCR2.4 RCR2.3 RCR2.2
FSBE
RCR2.1
MOSCRF
RCR2.0
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DS3120
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=35 Hex)
(MSB) LOTCMC SYMBOL LOTCMC TFPT TCPT POSITION TCR1.7 TSSE GB7S TFDLS TBL (LSB) TYEL
NAME AND DESCRIPTION Loss Of Transmit Clock Mux Control. Determines whether the transmit side formatter should switch to RCLK if the TCLK input should fail to transition (see Figure 1-1 for details). 0 = do not switch to RCLK if TCLK stops 1 = switch to RCLK if TCLK stops Transmit F-Bit Pass Through. (see note below) 0 = F bits sourced internally 1 = F bits sampled at TSER Transmit CRC Pass Through. (see note below) 0 = source CRC6 bits internally 1 = CRC6 bits sampled at TSER during F-bit time Software Signaling Insertion Enable. (see note below) 0 = no signaling is inserted in any channel 1 = signaling is inserted in all channels from the TS1-TS12 registers (the TTR registers can be used to block insertion on a channel by channel basis) Global Bit 7 Stuffing. (see note below) 0 = allow the TTR registers to determine which channels containing all zeros are to be Bit 7 stuffed 1 = force Bit 7 stuffing in all 0-byte channels regardless of how the TTR registers are programmed TFDL Register Select. (see note below) 0 = source FDL or Fs bits from the internal TFDL register (legacy FDL support mode) 1 = source FDL or Fs bits from the internal HDLC/BOC controller or TSER Transmit Blue Alarm. (see note below) 0 = transmit data normally 1 = transmit an unframed all one's code at TNRZ Transmit Yellow Alarm. (see note below) 0 = do not transmit yellow alarm 1 = transmit yellow alarm
TFPT
TCR1.6
TCPT
TCR1.5
TSSE
TCR1.4
GB7S
TCR1.3
TFDLS
TCR1.2
TBL
TCR1.1
TYEL
TCR1.0
NOTE:
For a description of how the bits in TCR1 affect the transmit side formatter, see Figure 20-5.
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DS3120
TCR2: TRANSMIT CONTROL REGISTER 2 (Address=36 Hex)
(MSB) 0 SYMBOL 0 0 0 0 0 TSIO 0 0 POSITION TCR2.7 TCR2.6 TCR2.5 TCR2.4 TCR2.3 TCR2.2 0 0 TSIO TD4YM (LSB) TB7ZS
NAME AND DESCRIPTION This control bit must be set to zero. This control bit must be set to zero. This control bit must be set to zero. This control bit must be set to zero. This control bit must be set to zero. TSYNC I/O Select. This bit should only be set to one in Modes 12 & 13; it should be set to zero in all other Modes. 0 = TSYNC is an input 1 = TSYNC is an output (Mode 12 & 13 only) Transmit Side D4 Yellow Alarm Select. 0 = zeros in bit 2 of all channels 1 = a one in the S-bit position of frame 12 Transmit Side Bit 7 Zero Suppression Enable. 0 = no stuffing occurs 1 = Bit 7 force to a one in channels with all zeros
TD4YM
TCR2.1
TB7ZS
TCR2.0
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DS3120
CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex)
(MSB) TESE SYMBOL TESE 1 RSAO POSITION CCR1.7 1 1 RESE PLB (LSB) FLB
NAME AND DESCRIPTION Transmit Elastic Store Enable. This bit should only be set to one in Modes 9 & 10; it should be set to zero in all other Modes. 0 = elastic store is bypassed 1 = elastic store is enabled (Modes 9 & 10 only) This control bit must be set to one. Receive Signaling All One's. This bit should not be enabled if hardware signaling is being utilized. See Section 10 for more details. 0 = allow robbed signaling bits to appear at RSER 1 = force all robbed signaling bits at RSER to one This control bit must be set to one. This control bit must be set to one. Receive Elastic Store Enable. This bit should only be set to one in Modes 9 & 10; it should be set to zero in all other Modes. 0 = elastic store is bypassed 1 = elastic store is enabled (Modes 9 & 10 only) Payload Loopback. 0 = loopback disabled 1 = loopback enabled Framer Loopback. 0 = loopback disabled 1 = loopback enabled
1 RSAO
CCR1.6 CCR1.5
1 1 RESE
CCR1.4 CCR1.3 CCR1.2
PLB
CCR1.1
FLB
CCR1.0
Payload Loopback
When CCR1.1 is set to a one, the DS3120 will be forced into Payload LoopBack (PLB). Normally, this loopback is only enabled when ESF framing is being performed but can be enabled also in D4 framing applications. In a PLB situation, the DS3120 will loop the 192 bits of payload data from the receive section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the DS3120. When PLB is enabled, the following will occur: 1. data will be transmitted from TNRZ synchronous with RCLK instead of TCLK or CTCLK 2. all of the receive side signals will continue to operate normally 3. data at the TSER, and TSIG pins is ignored.
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DS3120
Framer Loopback
When CCR1.0 is set to a one, the DS3120 will enter a Framer LoopBack (FLB) mode. This loopback is useful in testing and debugging applications. In FLB, the DS3120 will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur: 1. an unframed all one's code will be transmitted at TNRZ 2. data at RNRZ will be ignored 3. RSER, RSIG, and RSYNC will take on timing synchronous with TCLK instead of RCLK Please note that it is not acceptable to enable this loopback in Looped Timed Modes because this will cause an unstable condition.
CCR2: COMMON CONTROL REGISTER 2 (Address=38 Hex)
(MSB) TFM SYMBOL TFM 0 TSLC96 POSITION CCR2.7 TZSE RFM EXZS RSLC96 (LSB) RZSE
NAME AND DESCRIPTION Transmit Frame Mode Select. 0 = D4 framing mode 1 = ESF framing mode This control bit must be set to zero. Transmit SLC-96 / Fs-Bit Insertion Enable. Only set this bit to a one in D4 framing applications. Must be set to one to source the Fs pattern. See Section 15 for details. 0 = SLC-96/Fs-bit insertion disabled 1 = SLC-96/Fs-bit insertion enabled Transmit FDL Zero Stuffer Enable. Set this bit to zero if using the internal HDLC/BOC controller instead of the legacy support for the FDL. See Section 15 for details. 0 = zero stuffer disabled 1 = zero stuffer enabled Receive Frame Mode Select. 0 = D4 framing mode 1 = ESF framing mode EXcessive Zero (EXZ) Select. 0 = 16 consecutive zeros 1 = 8 consecutive zeros Receive SLC-96 Enable. Only set this bit to a one in D4/SLC- 96 framing applications. See Section 15 for details. 0 = SLC-96 disabled 1 = SLC-96 enabled Receive FDL Zero Destuffer Enable. Set this bit to zero if using the internal HDLC/BOC controller instead of the legacy support for the FDL. See Section 15 for details. 0 = zero destuffer disabled 1 = zero destuffer enabled
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0 TSLC96
CCR2.6 CCR2.5
TZSE
CCR2.4
RFM
CCR2.3
EXZS
CCR2.2
RSLC96
CCR2.1
RZSE
CCR2.0
DS3120
CCR3: COMMON CONTROL REGISTER 3 (Address=30 Hex)
(MSB) 0 SYMBOL 0 0 0 0 PDE 0 0 POSITION CCR3.7 CCR3.6 CCR3.5 CCR3.4 CCR3.3 0 PDE ECUS TLOOP (LSB) 0
NAME AND DESCRIPTION This control bit must be set to zero. This control bit must be set to zero. This control bit must be set to zero. This control bit must be set to zero. Pulse Density Enforcer Enable. 0 = disable transmit pulse density enforcer 1 = enable transmit pulse density enforcer Error Counter Update Select. See Section 8 for details. 0 = update error counters once a second 1 = update error counters every 42 ms (333 frames) Transmit Loop Code Enable. See Section 16 for details. 0 = transmit data normally 1 = replace normal transmitted data with repeating code as defined in TCD register This control bit must be set to zero.
ECUS
CCR3.2
TLOOP
CCR3.1
0
CCR3.0
Pulse Density Enforcer
The Framer always examines both the transmit and receive data streams for violations of the following rules which are required by ANSI T1.403: - no more than 15 consecutive zeros - at least N ones in each and every time window of 8 x (N +1) bits where N = 1 through 23 Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits respectively. When the CCR3.3 is set to one, the DS3120 will force the transmitted stream to meet this requirement no matter the content of the transmitted stream.
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DS3120
CCR4: COMMON CONTROL REGISTER 4 (Address=11 Hex)
(MSB) 0 SYMBOL 0 RPCSI RPCSI RFSA1 POSITION CCR4.7 CCR4.6 RFE RFF THSE TPCSI (LSB) TIRFS
NAME AND DESCRIPTION This control bit must be set to zero. Receive Per-Channel Stuffing Insert. See Sections 10 & 12 for more details. 0 = do not use RCHBLK to determine which channels should be stuffed to one. 1 = use RCHBLK to determine which channels should be stuffed to one. Receive Force Signaling All Ones. See Section 10 for more details. 0 = do not force extracted robbed-bit signaling bit positions to a one 1 = force extracted robbed-bit signaling bit positions to a one Receive Freeze Enable. See Section 10 for details. 0 = no freezing of receive signaling data will occur 1 = allow freezing of receive signaling data at RSIG. Receive Force Freeze. Freezes receive side signaling at RSIG; will override Receive Freeze Enable (RFE). See Section 10 for details. 0 = do not force a freeze event 1 = force a freeze event Transmit Hardware Signaling Insertion Enable. See Sections 10 & 12 for details. 0 = do not insert signaling from the TSIG pin into the data stream presented at the TSER pin. 1 = Insert the signaling from the TSIG pin into data stream presented at the TSER pin. Transmit Per-Channel Signaling Insert. See Section 10 for details. 0 = do not use TCHBLK to determine which channels should have signaling inserted from the TSIG pin. 1 = use TCHBLK to determine which channels should have signaling inserted from the TSIG pin. Transmit Idle Registers (TIR) Function Select. See Section 11 for timing details. 0 = TIRs define in which channels to insert idle code 1 = TIRs define in which channels to insert data from RSER (i.e., Per = Channel Loopback function)
RFSA1
CCR4.5
RFE
CCR4.4
RFF
CCR4.3
THSE
CCR4.2
TPCSI
CCR4.1
TIRFS
CCR4.0
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CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex)
(MSB) TJC SYMBOL TJC - - POSITION CCR5.7 TCM4 TCM3 TCM2 TCM1 (LSB) TCM0
NAME AND DESCRIPTION Transmit Japanese CRC6 Enable. 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC6 calculation Not Assigned. Must be set to zero when written. Not Assigned. Must be set to zero when written. Transmit Channel Monitor Bit 4. MSB of a channel decode that determines which transmit channel data will appear in the TDS0M register. See Section 9 for details. Transmit Channel Monitor Bit 3. Transmit Channel Monitor Bit 2. Transmit Channel Monitor Bit 1. Transmit Channel Monitor Bit 0. LSB of the channel decode.
- - TCM4
CCR5.6 CCR5.5 CCR5.4
TCM3 TCM2 TCM1 TCM0
CCR5.3 CCR5.2 CCR5.1 CCR5.0
CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex)
(MSB) RJC RESALGN TESALGN RCM4 RCM3 RCM2 RCM1 (LSB) RCM0
SYMBOL RJC
POSITION CCR6.7
NAME AND DESCRIPTION Receive Japanese CRC6 Enable. 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC6 calculation Receive Elastic Store Align. Setting this bit from a zero to a one may force the receive elastic store's write/read pointers to a minimum separation of half a frame. No action will be taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less then half a frame, the command will be executed and data will be disrupted. Should be toggled after 8MCLKI has been applied and is stable. Must be cleared and set again for a subsequent align. See Section 13 for details. Transmit Elastic Store Align. Setting this bit from a zero to a one may force the transmit elastic store's write/read pointers to a minimum separation of half a frame. No action will be taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less then half a frame, the command will be executed and data will be disrupted. Should be toggled after 8MCLKI has been applied and is stable. Must be cleared and set again for a subsequent align. See Section 13 for details. Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive channel data will appear in the RDS0M register. See Section 9 for details.
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RESALGN
CCR6.6
TESALGN
CCR6.5
RCM4
CCR6.4
DS3120
SYMBOL RCM3 RCM2 RCM1 RCM0
POSITION CCR6.3 CCR6.2 CCR6.1 CCR6.0
NAME AND DESCRIPTION Receive Channel Monitor Bit 3. Receive Channel Monitor Bit 2. Receive Channel Monitor Bit 1. Receive Channel Monitor Bit 0. LSB of the channel decode.
CCR7: COMMON CONTROL REGISTER 7 (Address=0A Hex)
(MSB) - SYMBOL - RLB RLB RESR POSITION CCR7.7 CCR7.6 TESR - - - (LSB) -
RESR
CCR7.5
TESR
CCR7.4
- - - -
CCR7.3 CCR7.2 CCR7.1 CCR7.0
NAME AND DESCRIPTION Not Assigned. Should be set to zero when written to. Remote Loopback. 0 = loopback disabled 1 = loopback enabled Receive Elastic Store Reset. Setting this bit from a zero to a one will force the receive elastic store to a depth of one frame. Receive data is lost during the reset. Should be toggled after 8MCLKI has been applied and is stable. Do not leave this bit set high. Transmit Elastic Store Reset. Setting this bit from a zero to a one will force the transmit elastic store to a depth of one frame. Transmit data is lost during the reset. Should be toggled after 8MCLKI has been applied and is stable. Do not leave this bit set high. Not Assigned. Should be set to zero when written to. Not Assigned. Should be set to zero when written to. Not Assigned. Should be set to zero when written to. Not Assigned. Should be set to zero when written to.
Remote Loopback
When CCR7.6 is set to a one, the DS3120 will be forced into Remote LoopBack (RLB). In this loopback, data input via the RNRZ signal will be transmitted back to TNRZ. Data will continue to pass through the receive side framer of the DS3120 as it would normally and the data from the transmit side formatter will be ignored. Please see Figure 1-1 for more details.
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7. STATUS AND INFORMATION REGISTERS
There is a set of nine registers per channel that contain information on the current real time status of a framer in the DS3120, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Registers 1 to 3 (RIR1/RIR2/RIR3) and a set of four registers for the onboard HDLC and BOC controller. The specific details on the four registers pertaining to the HDLC and BOC controller are covered in Section 15 but they operate the same as the other status registers in the DS3120 and this operation is described below. When a particular event has occurred (or is occurring), the appropriate bit in one of these nine registers will be set to a one. All of the bits in SR1, SR2, RIR1, RIR2, and RIR3 registers operate in a latched fashion. This means that if an event or an alarm occurs and a bit is set to a one in any of the registers, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again (or in the case of the RBL, RYEL, LRCL, and RLOS alarms, the bit will remain set if the alarm is still present). There are bits in the four HDLC and BOC status registers that are not latched and these bits are listed in Section 14. The user will always precede a read of any of the nine registers with a write. The byte written to the register will inform the DS3120 which bits the user wishes to read and have cleared. The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is written to a bit location, the read register will be updated with the latest information. When a zero is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status and information registers will be immediately followed by a read of the same register. The read result should be logically AND'ed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. This second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. This write-read- write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS3120 with higher-order software languages. The SR1, SR2, and HSR registers have the unique ability to initiate a hardware interrupt via the INT* output pin. Each of the alarms and events in the SR1, SR2, and HSR can be either masked or unmasked from the interrupt pin via the Interrupt Mask Register 1 (IMR1), Interrupt Mask Register 2 (IMR2), and HDLC Interrupt Mask Register (HIMR) respectively. The HIMR register is covered in Section 14. The Interrupt Status Registers (IMR1/2/3/4) can be used to determine which framer is requesting interrupt servicing. The interrupts caused by alarms in SR1 (namely RYEL, RCL, RBL, RLOS and LOTC) act differently than the interrupts caused by events in SR1 and SR2 (namely LUP, LDN, RSLIP, RMF, TMF, SEC, RFDL, TFDL, RMTCH, RAF, and RSC) and HIMR. The alarm caused interrupts will force the INT* pin low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the set/clear criteria in Table 7-1). The INT* pin will be allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the interrupt to occur even if the alarm is still present. The event caused interrupts will force the INT* pin low when the event occurs. The INT* pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
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Interrupt Status Registers
Interrupt Status Registers 1 to 4 report the real time status on the interrupts from each T1 framer. Figure 7-1 provides a visual description of the signal flow to each bit in the ISR1 register. The other ISR registers are similar.
ISR1: INTERRUPT STATUS REGISTER1 (Address 00 Hex when FS0 to FS4 = 11111)
(MSB) FR8 FR7 FR6 FR5 FR4 FR3 FR2 (LSB) FR1
ISR2: INTERRUPT STATUS REGISTER2 (Address 01 Hex when FS0 to FS4 = 11111)
(MSB) FR16 FR15 FR14 FR13 FR12 FR11 FR10 (LSB) FR9
ISR3: INTERRUPT STATUS REGISTER3 (Address 02 Hex when FS0 to FS4 = 11111)
(MSB) FR24 FR23 FR22 FR21 FR20 FR19 FR18 (LSB) FR17
ISR4: INTERRUPT STATUS REGISTER4 (Address 03 Hex when FS0 to FS4 = 11111)
(MSB) SYMBOL FRn (where n = 1 to 28) POSITION ISRi.j (where i = 1 to 4; j = 1 to 7) ISR4.j (where j = 4 to 7) FR28 FR27 FR26 (LSB) FR25
NAME AND DESCRIPTION FRAMER n (n = 1 to 28) INTERRUPT REQUEST. 0 = No interrupt request pending. 1 = Interrupt request pending. NOT ASSIGNED. Could be any value when read.
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Interrupt Status Register 1 Signal Flow Figure 7-1
Framer 8 HDLC Status Reg. (HSR) Status Reg. 2 (SR2) Status Reg. 1 (SR1) Framer 6 HDLC Status Reg. (HSR) Status Reg. 2 (SR2) Status Reg. 1 (SR1) Framer 4 HDLC Status Reg. (HSR) Status Reg. 2 (SR2) Status Reg. 1 (SR1) Framer 2 HDLC Status Reg. (HSR) Status Reg. 2 (SR2) Status Reg. 1 (SR1)
HDLC Interrupt Mask Reg. (HIMR)
Interrupt Mask Reg. 2 (IMR2)
Interrupt Mask Reg. 1 (IMR1)
HDLC Interrupt Mask Reg. (HIMR)
Interrupt Mask Reg. 2 (IMR2)
Interrupt Mask Reg. 1 (IMR1)
HDLC Interrupt Mask Reg. (HIMR)
Interrupt Mask Reg. 2 (IMR2)
Interrupt Mask Reg. 1 (IMR1)
HDLC Interrupt Mask Reg. (HIMR)
Interrupt Mask Reg. 2 (IMR2)
Interrupt Mask Reg. 1 (IMR1)
OR
OR
OR
OR
Framer 7 HDLC Status Reg. (HSR) Status Reg. 2 (SR2) Status Reg. 1 (SR1)
Framer 5 HDLC Status Reg. (HSR) Status Reg. 2 (SR2) Status Reg. 1 (SR1)
Framer 3 HDLC Status Reg. (HSR) Status Reg. 2 (SR2) Status Reg. 1 (SR1)
Framer 1 HDLC Status Reg. (HSR) Status Reg. 2 (SR2) Status Reg. 1 (SR1)
HDLC Interrupt Mask Reg. (HIMR)
Interrupt Mask Reg. 2 (IMR2)
Interrupt Mask Reg. 1 (IMR1)
HDLC Interrupt Mask Reg. (HIMR)
Interrupt Mask Reg. 2 (IMR2)
Interrupt Mask Reg. 1 (IMR1)
HDLC Interrupt Mask Reg. (HIMR)
Interrupt Mask Reg. 2 (IMR2)
Interrupt Mask Reg. 1 (IMR1)
HDLC Interrupt Mask Reg. (HIMR)
Interrupt Mask Reg. 2 (IMR2)
Interrupt Mask Reg. 1 (IMR1)
OR
OR
OR
OR
FR8
FR7
FR6
FR5
FR4
FR3
FR2
FR1
Interrupt Status Register 1 (ISR1)
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RIR1: RECEIVE INFORMATION REGISTER 1 (Address=22 Hex)
(MSB) COFA SYMBOL COFA 8ZD 8ZD 16ZD POSITION RIR1.7 RIR1.6 RESF RESE SEFE (LSB) FBE
NAME AND DESCRIPTION Change of Frame Alignment. Set when the last resync resulted in a change of frame or multiframe alignment. Eight Zero Detect. Set when a string of at least eight consecutive zeros (regardless of the length of the string) have been received at RPOS and RNEG. Sixteen Zero Detect. Set when a string of at least sixteen consecutive zeros (regardless of the length of the string) have been received at RPOS and RNEG. Receive Elastic Store Full. Set when the receive elastic store buffer fills and a frame is deleted. Receive Elastic Store Empty. Set when the receive elastic store buffer empties and a frame is repeated. Severely Errored Framing Event. Set when 2 out of 6 framing bits (Ft or FPS) are received in error. This status bit is not assigned and could be any value when read. Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing bit is received in error.
16ZD
RIR1.5
RESF RESE SEFE FBE
RIR1.4 RIR1.3 RIR1.2 RIR1.1 RIR1.0
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RIR2: RECEIVE INFORMATION REGISTER 2 (Address=31 Hex)
(MSB) RLOSC SYMBOL RLOSC RCLC TESF TESE TSLIP RBLC RPDV RCLC TESF POSITION RIR2.7 RIR2.6 RIR2.5 RIR2.4 RIR2.3 RIR2.2 RIR2.1 TESE TSLIP RBLC RPDV (LSB) TPDV
NAME AND DESCRIPTION Receive Loss of Sync Clear. Set when the framer achieves synchronization; will remain set until read. Receive Carrier Loss Clear. Set when the carrier signal is restored; will remain set until read. See Table 7-1. Transmit Elastic Store Full. Set when the transmit elastic store buffer fills and a frame is deleted. Transmit Elastic Store Empty. Set when the transmit elastic store buffer empties and a frame is repeated. Transmit Elastic Store Slip Occurrence. Set when the transmit elastic store has either repeated or deleted a frame. Receive Blue Alarm Clear. Set when the Blue Alarm (AIS) is no longer detected; will remain set until read. See Table 7-1. Receive Pulse Density Violation. Set when the receive data stream does not meet the ANSI T1.403 requirements for pulse density. Transmit Pulse Density Violation. Set when the transmit data stream does not meet the ANSI T1.403 requirements for pulse density.
TPDV
RIR2.0
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RIR3: RECEIVE INFORMATION REGISTER 3 (Address=10 Hex)
(MSB) - SYMBOL - - - LORC - - - RAIS-CI - - POSITION RIR3.7 RIR3.6 RIR3.5 RIR3.4 RIR3.3 RIR3.2 RIR3.1 RIR3.0 LORC - - - (LSB) RAIS-CI
NAME AND DESCRIPTION Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Loss of Receive Clock. Set when the RCLK signal has not transitioned for at least 2 us (3 us 1 us). Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Receive AIS-CI Detect. Set when the AIS-CI pattern is detected.
SR1: STATUS REGISTER 1 (Address=20 Hex)
(MSB) LUP SYMBOL LUP LDN LOTC POSITION SR1.7 RSLIP RBL RYEL RCL (LSB) RLOS
NAME AND DESCRIPTION Loop Up Code Detected. Set when the loop up code as defined in the RUPCD register is being received. See Section 16 for details. Loop Down Code Detected. Set when the loop down code as defined in the RDNCD register is being received. See Section 16 for details. Loss of Transmit Clock. Set when the TCLK pin has not transitioned for one channel time (or 5.2 us). Will force transmit side formatter to switch to RCLK if so enabled via TCR1.7. Receive Elastic Store Slip Occurrence. Set when the receive elastic store has either repeated or deleted a frame. Receive Blue Alarm. Set when an unframed all one's code is received at RNRZ. Receive Yellow Alarm. Set when a yellow alarm is received at RNRZ. Receive Carrier Loss. Set when a red alarm is received at RNRZ. Receive Loss of Sync. Set when the device is not synchronized to the receive T1 stream.
LDN
SR1.6
LOTC
SR1.5
RSLIP RBL RYEL RCL RLOS
SR1.4 SR1.3 SR1.2 SR1.1 SR1.0
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ALARM CRITERIA Table 7-1
ALARM Blue Alarm (AIS) (see note 1 below) Yellow Alarm (RAI) 1. D4 bit 2 mode(RCR2.2=0) SET CRITERIA when over a 3 ms window, 5 or less zeros are received when bit 2 of 256 consecutive channels is set to zero for at least 254 occurrences when the 12th framing bit is set to one for two consecutive occurrences CLEAR CRITERIA when over a 3 ms window, 6 or more zeros are received when bit 2 of 256 consecutive channels is set to zero for less than 254 occurrences when the 12th framing bit is set to zero for two consecutive occurrences
2. D4 12th F-bit mode (RCR2.2=1; this mode is also referred to as the "Japanese Yellow Alarm") 3. ESF mode
when 16 consecutive patterns of 00FF appear in the FDL when 192 consecutive zeros are received
Red Alarm (RCL) (this alarm is also referred to as Loss Of Signal)
when 14 or less patterns of 00FF hex out of 16 possible appear in the FDL when 14 or more ones out of 112 possible bit positions are received starting with the first one received
NOTES:
1. The definition of Blue Alarm (or Alarm Indication Signal) is an unframed all ones signal. Blue alarm detectors should be able to operate properly in the presence of a 10-3 error rate and they should not falsely trigger on a framed all ones signal. The blue alarm criteria in the DS3120 has been set to achieve this performance. It is recommended that the RBL bit be qualified with the RLOS bit. 2. ANSI specifications use a different nomenclature than the DS3120 does; the following terms are equivalent: RBL = AIS RCL = LOS RLOS = LOF RYEL = RAI
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SR2: STATUS REGISTER 2 (Address=21 Hex)
(MSB) RMF SYMBOL RMF TMF SEC TMF SEC POSITION SR2.7 SR2.6 SR2.5 RFDL TFDL RMTCH RAF (LSB) RSC
NAME AND DESCRIPTION Receive Multiframe. Set on receive multiframe boundaries. Transmit Multiframe. Set on transmit multiframe boundaries. One Second Timer. Set on increments of one second based on RCLK; will be set in increments of 999 ms, 999 ms, and 1002 ms every 3 seconds (or every 42 ms if CCR3.2 = 1). Receive FDL Buffer Full. Set when the receive FDL buffer (RFDL) fills to capacity (8 bits). Transmit FDL Buffer Empty. Set when the transmit FDL buffer (TFDL) empties. Receive FDL Match Occurrence. Set when the RFDL matches either RMTCH1 or RMTCH2. Receive FDL Abort. Set when eight consecutive one's are received in the FDL. Receive Signaling Change. Set when the DS3120 detects a change of state in any of the robbed-bit signaling bits.
RFDL TFDL RMTCH RAF RSC
SR2.4 SR2.3 SR2.2 SR2.1 SR2.0
IMR1: INTERRUPT MASK REGISTER 1 (Address=7F Hex)
(MSB) LUP SYMBOL LUP LDN LOTC POSITION IMR1.7 SLIP RBL RYEL RCL (LSB) RLOS
NAME AND DESCRIPTION Loop Up Code Detected. 0 = interrupt masked 1 = interrupt enabled Loop Down Code Detected. 0 = interrupt masked 1 = interrupt enabled Loss of Transmit Clock. 0 = interrupt masked 1 = interrupt enabled Elastic Store Slip Occurrence. 0 = interrupt masked 1 = interrupt enabled Receive Blue Alarm. 0 = interrupt masked 1 = interrupt enabled Receive Yellow Alarm. 0 = interrupt masked 1 = interrupt enabled
LDN
IMR1.6
LOTC
IMR1.5
SLIP
IMR1.4
RBL
IMR1.3
RYE
IMR1.2
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SYMBOL RCL
POSITION IMR1.1
NAME AND DESCRIPTION Receive Carrier Loss. 0 = interrupt masked 1 = interrupt enabled Receive Loss of Sync. 0 = interrupt masked 1 = interrupt enabled
RLOS
IMR1.0
IMR2: INTERRUPT MASK REGISTER 2 (Address=6F Hex)
(MSB) RMF SYMBOL RMF TMF SEC POSITION IMR2.7 RFDL TFDL RMTCH RAF (LSB) RSC
NAME AND DESCRIPTION Receive Multiframe. 0 = interrupt masked 1 = interrupt enabled Transmit Multiframe. 0 = interrupt masked 1 = interrupt enabled One Second Timer. 0 = interrupt masked 1 = interrupt enabled Receive FDL Buffer Full. 0 = interrupt masked 1 = interrupt enabled Transmit FDL Buffer Empty. 0 = interrupt masked 1 = interrupt enabled Receive FDL Match Occurrence. 0 = interrupt masked 1 = interrupt enabled Receive FDL Abort. 0 = interrupt masked 1 = interrupt enabled Receive Signaling Change. 0 = interrupt masked 1 = interrupt enabled
TMF
IMR2.6
SEC
IMR2.5
RFDL
IMR2.4
TFDL
IMR2.3
RMTCH
IMR2.2
RAF
IMR2.1
RSC
IMR2.0
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8. ERROR COUNT REGISTERS
There are a set of three counters in each framer that record EXcessive Zeros (EXZ), errors in the CRC6 code words, framing bit errors, and number of multiframes that the device is out of receive synchronization. Each of these three counters are automatically updated on either one second boundaries (CCR3.2=0) or every 42 ms (CCR3.2=1) as determined by the timer in Status Register 2 (SR2.5). Hence, these registers contain performance data from either the previous second or the previous 42 ms. The user can use the interrupt from the one second (or 42 ms) timer to determine when to read these registers. The user has a full second (or 42 ms) to read the counters before the data is lost. All three counters will saturate at their respective maximum counts and they will not rollover.
Line Code Violation Count Register (LCVCR)
Line Code Violation Count Register 1 (LCVCR1) is the most significant word and LCVCR2 is the least significant word of a 16-bit counter that records code violations (CVs). CVs are defined as EXcessive Zeros (EXZ). See Table 8-1 for details of exactly what the LCVCRs count This counter is always enabled; it is not disabled during receive loss of synchronization (RLOS=1) conditions.
LCVCR1: LINE CODE VIOLATION COUNT REGISTER 1 (Address = 23 Hex) LCVCR2: LINE CODE VIOLATION COUNT REGISTER 2 (Address = 24 Hex)
(MSB) LCV15 LCV7 LCV14 LCV6 LCV13 LCV5 POSITION LCVCR1.7 LCVCR2.0 LCV12 LCV4 LCV11 LCV3 LCV10 LCV2 LCV9 LCV1 (LSB) LCV8 LCV0 LCVCR1 LCVCR2
SYMBOL LCV15 LCV0
NAME AND DESCRIPTION MSB of the 16-bit code violation count LSB of the 16-bit code violation count
LINE CODE VIOLATION COUNTING ARRANGEMENTS Table 8-1
EXcessive Zero Select (CCR2.2) 0 1 WHAT IS COUNTED IN THE LCVCRs 16 consecutive zero occurrences 8 consecutive zeros occurrences
Path Code Violation Count Register (PCVCR)
When the receive side of a framer is set to operate in the ESF framing mode (CCR2.3=1), PCVCR will automatically be set as a 12-bit counter that will record errors in the CRC6 code words. When set to operate in the D4 framing mode (CCR2.3=0), PCVCR will automatically count errors in the Ft framing bit position. Via the RCR2.1 bit, a framer can be programmed to also report errors in the Fs framing bit position. The PCVCR will be disabled during receive loss of synchronization (RLOS=1) conditions. See Table 8-2 for a detailed description of exactly what errors the PCVCR counts.
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PCVCR1: PATH VIOLATION COUNT REGISTER 1 (Address = 25 Hex) PCVCR2: PATH VIOLATION COUNT REGISTER 2 (Address = 26 Hex)
(MSB) (note 1) CRC/ FB7 (note 1) CRC/ FB6 (note 1) CRC/ FB5 POSITION PCVCR1.3 PCVCR2.0 (note 1) CRC/ FB4 CRC/ FB11 CRC/ FB3 CRC/ FB10 CRC/ FB2 CRC/ FB9 CRC/ FB1 (LSB) CRC/ FB8 CRC/ FB0 PCVCR1 PCVCR2
SYMBOL CRC/FB11 CRC/FB0
NAME AND DESCRIPTION MSB of the 12-Bit CRC6 Error or Frame Bit Error Count (note #2) LSB of the 12-Bit CRC6 Error or Frame Bit Error Count (note #2)
NOTES:
1. The upper nibble of the counter at address 25h is used by the Multiframes Out of Sync Count Register 3. PCVCR counts either errors in CRC code words (in the ESF framing mode; CCR2.3=1) or errors in the framing bit position (in the D4 framing mode; CCR2.3=0).
PATH CODE VIOLATION COUNTING ARRANGEMENTS Table 8-2
FRAMING MODE (CCR2.3) D4 D4 ESF COUNT Fs ERRORS? (RCR2.1) no yes don't care WHAT IS COUNTED IN THE PCVCRs errors in the Ft pattern errors in both the Ft & Fs patterns errors in the CRC6 code words
MULTIFRAMES OUT OF SYNC COUNT REGISTER (MOSCR)
Normally the MOSCR is used to count the number of multiframes that the receive synchronizer is out of sync (RCR2.0=1). This number is useful in ESF applications needing to measure the parameters Loss Of Frame Count (LOFC) and ESF Error Events as described in AT&T publication TR54016. When the MOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOS=1) conditions. The MOSCR has alternate operating mode whereby it will count either errors in the Ft framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF mode). When the MOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOS = 1) conditions. See Table 8-3 for a detailed description of what the MOSCR is capable of counting.
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MOSCR1: MULTIFRAMES OUT OF SYNC COUNT REGISTER 1 (Address = 25 Hex) MOSCR2: MULTIFRAMES OUT OF SYNC COUNT REGISTER 2 (Address = 27 Hex)
(MSB) MOS/ FB11 MOS/ FB7 MOS/ FB10 MOS/ FB6 MOS/ FB9 MOS/ FB5 POSITION MOSCR1.7 MOSCR2.0 MOS/ FB8 MOS/ FB4 (note 1) MOS/ FB3 (note 1) MOS/ FB2 (note 1) MOS/ FB1 (LSB) (note 1) MOS/ FB0 MOSCR 1 MOSCR 2
SYMBOL MOS/FB11 MOS/FB0
NAME AND DESCRIPTION MSB of the 12-Bit Multiframes Out of Sync or F-Bit Error Count (note #2) LSB of the 12-Bit Multiframes Out of Sync or F-Bit Error Count (note #2)
NOTES:
1. The lower nibble of the counter at address 25h is used by the Path Code Violation Count Register 2. MOSCR counts either errors in framing bit position (RCR2.0=0) or the number of multiframes out of sync (RCR2.0=1)
MULTIFRAMES OUT OF SYNC COUNTING ARRANGEMENTS Table 8-3
FRAMING MODE (CCR2.3) D4 D4 ESF ESF COUNT MOS OR F-BIT ERRORS (RCR2.0) MOS F-Bit MOS F-Bit WHAT IS COUNTED IN THE MOSCRs number of multiframes out of sync errors in the Ft pattern number of multiframes out of sync errors in the FPS pattern
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9. DS0 MONITORING FUNCTION
Each framer in the DS3120 has the ability to monitor one DS0 64 Kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR5 register. In the receive direction, the RCM0 to RCM4 bits in the CCR6 register need to be properly set. The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor (TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode of the appropriate T1 channel. Channels 1 through 24 map to register values 0 through 23. For example, if DS0 channel 6 (timeslot 5) in the transmit direction and DS0 channel 15 (timeslot 14) in the receive direction needed to be monitored, then the following values would be programmed into CCR5 and CCR6: TCM4 = 0 TCM3 = 0 TCM2 = 1 TCM1 = 0 TCM0 = 1 RCM4 = 0 RCM3 = 1 RCM2 = 1 RCM1 = 1 RCM0 = 0
CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex)
[repeated here from Section 6 for convenience] (MSB) TJC - - TCM4 SYMBOL TJC - - TCM4 POSITION CCR5.7 CCR5.5 CCR5.5 CCR5.4 TCM3 TCM2 TCM1 (LSB) TCM0
NAME AND DESCRIPTION Transmit Japanese CRC Enable. See Section 6 for details. Not Assigned. Must be set to zero when written. Not Assigned. Must be set to zero when written. Transmit Channel Monitor Bit 4. MSB of a channel decode that determines which transmit DS0 channel data will appear in the TDS0M register. Transmit Channel Monitor Bit 3. Transmit Channel Monitor Bit 2. Transmit Channel Monitor Bit 1. Transmit Channel Monitor Bit 0. LSB of the channel decode that determines which transmit DS0 channel data will appear in the TDS0M register.
TCM3 TCM2 TCM1 TCM0
CCR5.3 CCR5.2 CCR5.1 CCR5.0
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TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address=1A Hex)
(MSB) B1 SYMBOL B1 B2 B3 B4 B5 B6 B7 B8 B2 B3 POSITION TDS0M.7 TDS0M.6 TDS0M.5 TDS0M.4 TDS0M.3 TDS0M.2 TDS0M.1 TDS0M.0 B4 B5 B6 B7 (LSB) B8
NAME AND DESCRIPTION Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be transmitted). Transmit DS0 Channel Bit 2. Transmit DS0 Channel Bit 3. Transmit DS0 Channel Bit 4. Transmit DS0 Channel Bit 5. Transmit DS0 Channel Bit 6. Transmit DS0 Channel Bit 7. Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last bit to be transmitted).
CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex)
[repeated here from Section 6 for convenience] (MSB) RJC RESALGN TESALGN RCM4 SYMBOL RJC POSITION CCR6.7 RCM3 RCM2 RCM1 (LSB) RCM0
NAME AND DESCRIPTION Receive Japanese CRC6 Enable. 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC6 calculation Receive Elastic Store Align. Setting this bit from a zero to a one will force the receive elastic store's write/read pointers to a minim separation of half a frame. If pointer separation is already greater than half a frame, setting this bit will have no effect. Should be toggled after 8MCLKI has been applied and is stable. Must be cleared and set again for a subsequent align. See Section 13 for details. Transmit Elastic Store Align. Setting this bit from a zero to a one will force the transmit elastic store's write/read pointers to a minimum separation of half a frame. If pointer separation is already greater than half a frame, setting this bit will have no effect. Should be toggled after 8MCLKI has been applied and is stable. Must be cleared and set again for a subsequent align. See Section 13 for details. Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive channel data will appear in the RDS0M register. Receive Channel Monitor Bit 3. Receive Channel Monitor Bit 2. Receive Channel Monitor Bit 1.
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RESALGN
CCR6.6
TESALGN
CCR6.5
RCM4
CCR6.4
RCM3 RCM2 RCM1
CCR6.3 CCR6.2 CCR6.1
DS3120
SYMBOL RCM0
POSITION CCR6.0
NAME AND DESCRIPTION Receive Channel Monitor Bit 0. LSB of the channel decode.
RDS0M: RECEIVE DS0 MONITOR REGISTER (Address=1F Hex)
(MSB) B1 SYMBOL B1 B2 B3 B4 B5 B6 B7 B8 B2 B3 POSITION RDS0M.7 RDS0M.6 RDS0M.5 RDS0M.4 RDS0M.3 RDS0M.2 RDS0M.1 RDS0M.0 B4 B5 B6 B7 (LSB) B8
NAME AND DESCRIPTION Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit received). Receive DS0 Channel Bit 2. Receive DS0 Channel Bit 3. Receive DS0 Channel Bit 4. Receive DS0 Channel Bit 5. Receive DS0 Channel Bit 6. Receive DS0 Channel Bit 7. Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit received).
10.
SIGNALING OPERATION
Each framer in the DS3120 contains provisions for both processor based (i.e., software based) signaling bit access and for hardware based access. Both the processor based access and the hardware based access can be used simultaneously if necessary. The processor based signaling is covered in Section 10.1 and the hardware based signaling is covered in Section 10.2. Hardware based signaling is only available in Modes 5 through 10. See Section 3 for more details on the different modes of operation for the DS3120. Processor based signaling is available in all modes of operation.
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10.1 PROCESSOR BASED SIGNALING
The robbed-bit signaling bits embedded in the T1 stream can be extracted from the receive stream and inserted into the transmit stream by each framer. There is a set of 12 registers for the receive side (RS1 to RS12) and 12 registers on the transmit side (TS1 to TS12). The signaling registers are detailed below. The CCR1.5 bit is used to control the robbed signaling bits as they appear at RSER. If CCR1.5 is set to zero, then the robbed signaling bits will appear at the RSER pin in their proper position as they are received. If CCR1.5 is set to a one, then the robbed signaling bit positions will be forced to a one at RSER. If hardware based signaling is being used, then CCR1.5 must be set to zero.
RS1 TO RS12: RECEIVE SIGNALING REGISTERS (Address=60 to 6B Hex)
(MSB) A(8) A(16) A(24) B(8) B(16) B(24) A/C(8) A/C(16) A/C(24) B/D(8) B/D(16) B/D(24) A(7) A(15) A(23) B(7) B(15) B(23) A/C(7) A/C(15) A/C(23) B/D(7) B/D(15) B/D(23) A(6) A(14) A(22) B(6) B(14) B(22) A/C(6) A/C(14) A/C(22) B/D(6) B/D(14) B/D(22) A(5) A(13) A(21) B(5) B(13) B(21) A/C(5) A/C(13) A/C(21) B/D(5) B/D(13) B/D(21) A(4) A(12) A(20) B(4) B(12) B(20) A/C(4) A/C(12) A/C(20) B/D(4) B/D(12) B/D(20) A(3) A(11) A(19) B(3) B(11) B(19) A/C(3) A/C(11) A/C(19) B/D(3) B/D(11) B/D(19) A(2) A(10) A(18) B(2) B(10) B(18) A/C(2) A/C(10) A/C(18) B/D(2) B/D(10) B/D(18) (LSB) A(1) A(9) A(17) B(1) B(9) B(17) A/C(1) A/C(9) A/C(17) B/D(1) B/D(9) B/D(17) RS1 (60) RS2 (61) RS3 (62) RS4 (63) RS5 (64) RS6 (65) RS7 (66) RS8 (67) RS9 (68) RS10 (69) RS11 (6A) RS12 (6B)
SYMBOL D(24) A(1)
POSITION RS12.7 RS1.0
NAME AND DESCRIPTION Signaling Bit D in Channel 24 Signaling Bit A in Channel 1
Each Receive Signaling Register (RS1 to RS12) reports the incoming robbed bit signaling from eight DS0 channels. In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C, and D). In the D4 framing mode, there are only two signaling bits per channel (A and B). In the D4 framing mode, the framer will replace the C and D signaling bit positions with the A and B signaling bits from the previous multiframe. Hence, whether the framer is operated in either framing mode, the user needs only to retrieve the signaling bits every 3 ms. The bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the signaling bits. The Receive Signaling Registers are frozen and not updated during a loss of sync condition (SR1.0=1). They will contain the most recent signaling information before the "OOF" occurred. The signaling data reported in RS1 to RS12 is also available at the RSIG and RSER signals. A change in the signaling bits from one multiframe to the next will cause the RSC status bit (SR2.0) to be set. The user can enable the INT* pin to toggle low upon detection of a change in signaling by setting the IMR2.0 bit. Once a signaling change has been detected, the user has at least 2.75 ms to read the data out of the RS1 to RS12 registers before the data will be lost.
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TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (Address=70 to 7B Hex)
(MSB) A(8) A(16) A(24) B(8) B(16) B(24) A/C(8) A/C(16) A/C(24) B/D(8) B/D(16) B/D(24) A(7) A(15) A(23) B(7) B(15) B(23) A/C(7) A/C(15) A/C(23) B/D(7) B/D(15) B/D(23) A(6) A(14) A(22) B(6) B(14) B(22) A/C(6) A/C(14) A/C(22) B/D(6) B/D(14) B/D(22) A(5) A(13) A(21) B(5) B(13) B(21) A/C(5) A/C(13) A/C(21) B/D(5) B/D(13) B/D(21) A(4) A(12) A(20) B(4) B(12) B(20) A/C(4) A/C(12) A/C(20) B/D(4) B/D(12) B/D(20) A(3) A(11) A(19) B(3) B(11) B(19) A/C(3) A/C(11) A/C(19) B/D(3) B/D(11) B/D(19) A(2) A(10) A(18) B(2) B(10) B(18) A/C(2) A/C(10) A/C(18) B/D(2) B/D(10) B/D(18) (LSB) A(1) A(9) A(17) B(1) B(9) B(17) A/C(1) A/C(9) A/C(17) B/D(1) B/D(9) B/D(17) TS1 (70) TS2 (71) TS3 (72) TS4 (73) TS5 (74) TS7 (75) TS7 (76) TS8 (77) TS9 (78) TS10 (79) TS11 (7A) TS12 (7B)
SYMBOL D(24) A(1)
POSITION TS12.7 TS1.0
NAME AND DESCRIPTION Signaling Bit D in Channel 24 Signaling Bit A in Channel 1
Each Transmit Signaling Register (TS1 to TS12) contains the Robbed Bit signaling for eight DS0 channels that will be inserted into the outgoing stream if enabled to do so via TCR1.4. In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C, and D). On multiframe boundaries, the framer will load the values present in the Transmit Signaling Register into an outgoing signaling shift register that is internal to the device. The user can utilize the Transmit Multiframe Interrupt in Status Register 2 (SR2.6) to know when to update the signaling bits. In the ESF framing mode, the interrupt will come every 3 ms and the user has a full 3 ms to update the TSRs. In the D4 framing mode, there are only two signaling bits per channel (A and B). However in the D4 framing mode, the framer uses the C and D bit positions as the A and B bit positions for the next multiframe. The framer will load the values in the TSRs into the outgoing shift register every other D4 multiframe.
10.2 HARDWARE BASED SIGNALING Note:
Hardware Based Signaling requires access to the TSIG and RSIG signals which are only available in Modes 5 to 10. See Section 3 for more details on the various modes of operation in the DS3120.
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Receive Side
In hardware based signaling, the device extracts the signaling bits from the receive data stream and buffers them over a four multiframe depth and then outputs them in a serial PCM fashion on a channel- by-channel basis at the RSIG output. In the ESF framing mode, the ABCD signaling bits are output on RSIG in the lower nibble of each channel. The RSIG data is updated once a multiframe (3 ms) unless a freeze is in effect. In the D4 framing mode, the AB signaling bits are output twice on RSIG in the lower nibble of each channel. Hence, bits 5 and 6 contain the same data as bits 7 and 8 respectively in each channel. The RSIG data is updated once a multiframe (1.5 ms) unless a freeze is in effect. See the timing diagrams in Section 20 for some examples. In hardware based signaling, the user has the option to replace all of the extracted robbed-bit signaling bit positions with ones. This option is enabled via the RFSA1 control bit (CCR4.5) and it can be invoked on a per-channel basis by setting the RPCSI control bit (CCR4.6) high and then programming RCHBLK appropriately just like the per-channel signaling re-insertion operates. How to control the operation of RCHBLK is covered in Section 12. The signaling data in the four multiframe buffer will be frozen in a known good state upon either a loss of synchronization (OOF event), carrier loss, or frame slip. This action meets the requirements of BellCore TR- TSY-000170 for signaling freezing. To allow this freeze action to occur, the RFE control bit (CCR4.4) should be set high. The user can force a freeze by setting the RFF control bit (CCR4.3) high. The four multiframe buffer provides a three multiframe delay in the signaling bits provided at the RSIG pin. When freezing is enabled (RFE=1), the signaling data will be held in the last known good state until the corrupting error condition subsides. When the error condition subsides, the signaling data will be held in the old state for at least an additional 9 ms (or 4.5 ms in D4 framing mode) before being allowed to be updated with new signaling data.
Transmit Side
Via the THSE control bit (CCR4.2), the framer can be set up to take the signaling data presented at the TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The user has the ability to control which channels are to have signaling data from the TSIG pin inserted into them on a channel-by-channel basis by setting the TPCSI control bit (CCR4.1) high. When TPCSI is enabled, channels in which the TCHBLK signal has been programmed to be set high in, will not have signaling data from the TSIG pin inserted into them. How to control the operation of TCHBLK is covered in Section 12.
11.
PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK
Each framer in the DS3120 can replace data on a channel-by-channel basis in both the transmit and receive directions. The transmit direction is from the backplane to the T1 line and is covered in Section 11.1. The receive direction is from the T1 line to the backplane and is covered in Section 11.2.
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11.1 TRANSMIT SIDE CODE GENERATION
In the transmit direction there are two methods by which channel data from the backplane can be overwritten with data generated by the framer. The first method which is covered in Section 11.1.1 only allows the same 8-bit value to be placed in one or more of the 24 DS0 channels but it also has an alternate function to enable a per-channel loopback feature. The second method which is covered in Section 11.1.2 allows a different 8-bit value to be placed in each of the 24 DS0 channels.
11.1.1
Simple Idle Code Insertion and Per-Channel Loopback
The first method involves using the Transmit Idle Registers (TIR1/2/3) to determine which of the 24 DS0 channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR). This method allows the same 8-bit code to be placed into any of the 24 T1 channels. If this method is used, then the CCR4.0 control bit must be set to zero. Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3) represent a DS0 channel in the outgoing frame. When these bits are set to a one, the corresponding channel will transmit the Idle Code contained in the Transmit Idle Definition Register (TIDR). Robbed bit signaling and Bit 7 stuffing will occur over the programmed Idle Code unless the DS0 channel is made transparent by the Transmit Transparency Registers. The Transmit Idle Registers (TIRs) have an alternate function that allow them to define a Per-Channel LoopBack (PCLB). If the TIRFS control bit (CCR4.0) is set to one, then the TIRs will determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off of the T1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must be synchronized. Hence, Per-Channel LoopBack (PCLB) is only functional in the Loop Timed Modes (i.e., Modes 1, 2, 5, 6, and 9)
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address=3C to 3E Hex)
[Also used for Per-Channel Loopback] (MSB) CH8 CH7 CH6 CH5 CH16 CH15 CH14 CH13 CH24 CH23 CH22 CH21 SYMBOLS CH1 - 24 POSITIONS TIR1.0 - 3.7 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 CH9 CH17 TIR1 (3C) TIR2 (3D) TIR3 (3E)
NAME AND DESCRIPTION Transmit Idle Code Insertion Control Bits. 0 = do not insert the Idle Code in the TIDR into this channel 1 = insert the Idle Code in the TIDR into this channel
NOTE:
If CCR4.0=1, then a zero in the TIRs implies that channel data is to be sourced from TSER and a one implies that channel data is to be sourced from the output of the receive side framer (i.e., Per-Channel Loopback; see Figure 1-1).
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TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=3F Hex)
(MSB) TIDR7 SYMBOL TIDR7 TIDR0 TIDR6 TIDR5 POSITION TIDR.7 TIDR.0 TIDR4 TIDR3 TIDR2 TIDR1 (LSB) TIDR0
NAME AND DESCRIPTION MSB of the Idle Code (this bit is transmitted first) LSB of the Idle Code (this bit is transmitted last)
11.1.2
Per-Channel Code Insertion
The second method involves using the Transmit Channel Control Registers (TCC1/2/3) to determine which of the 24 T1 channels should be overwritten with the code placed in the Transmit Channel Registers (TC1 to TC24). This method is more flexible than the first in that it allows a different 8-bit code to be placed into each of the 24 T1 channels.
TC1 TO TC24: TRANSMIT CHANNEL REGISTERS (Address=40 to 4F and 50 to 57 Hex)
(for brevity, only channel one is shown; see Table 4-1 for other register address) (MSB) C7 C6 C5 C4 C3 C2 C1 SYMBOL C7 C0 POSITION TC1.7 TC1.0 NAME AND DESCRIPTION MSB of the Code (this bit is transmitted first) LSB of the Code (this bit is transmitted last) (LSB) C0 TC1 (50)
TCC1/TCC2/TCC3: TRANSMIT CHANNEL CONTROL REGISTER (Address=16 to 18 Hex)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITION TCC1.0 - 3.7 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 CH9 CH17 TCC1 (16) TCC2 (17) TCC3 (18)
SYMBOL CH1 - 24
NAME AND DESCRIPTION Transmit Code Insertion Control Bits 0 = do not insert data from the TC register into the transmit data stream 1 = insert data from the TC register into the transmit data stream
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11.2 RECEIVE SIDE CODE GENERATION
In the receive direction there are also two methods by which channel data to the backplane can be overwritten with data generated by the framer. The first method which is covered in Section 11.2.1 while the second method is covered in Section 11.2.2.
11.2.1
Simple Code Insertion
The first method on the receive side involves using the Receive Mark Registers (RMR1/2/3) to determine which of the 24 T1 channels should be overwritten with either a 7Fh idle code or with a digital milliwatt pattern. The RCR2.7 bit will determine which code is used. The digital milliwatt code is an 8 byte repeating pattern that represents a 1 kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the RMRs, represents a particular channel. If a bit is set to a one, then the receive data in that channel will be replaced with one of the two codes. If a bit is set to zero, no replacement occurs.
RMR1/RMR2/RMR3: RECEIVE MARK REGISTERS (Address=2D to 2F Hex)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 CH9 CH17 RMR1(2D) RMR2(2E) RMR3(2F)
SYMBOLS CH1 - 24
POSITIONS RMR1.0 - 3.7
NAME AND DESCRIPTION Receive Channel Mark Control Bits 0 =do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with either the idle code or the digital milliwatt code (depends on the RCR2.7 bit)
11.2.2
Per-Channel Code Insertion
The second method involves using the Receive Channel Control Registers (RCC1/2/3) to determine which of the 24 T1 channels off of the T1 line and going to the backplane should be overwritten with the code placed in the Receive Channel Registers (RC1 to RC24). This method is more flexible than the first in that it allows a different 8-bit code to be placed into each of the 24 T1 channels.
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RC1 TO RC24: RECEIVE CHANNEL REGISTERS (Address=58 to 5F and 80 to 8F Hex)
(for brevity, only channel one is shown; see Table 4-1 for other register address) (MSB) C7 C6 C5 C4 C3 C2 C1 SYMBOL C7 C0 POSITION RC1.7 RC1.0 NAME AND DESCRIPTION MSB of the Code (this bit is sent first to the backplane) LSB of the Code (this bit is sent last to the backplane) (LSB) C0 RC1 (80)
RCC1/RCC2/RCC3: RECEIVE CHANNEL CONTROL REGISTER (Address=1B to 1D Hex)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITION RCC1.0 - 3.7 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 CH9 CH17 RCC1 (1B) RCC2 (1C) RCC3 (1D)
SYMBOL CH1 - 24
NAME AND DESCRIPTION Receive Code Insertion Control Bits 0 = do not insert data from the RC register into the receive data stream 1 = insert data from the RC register into the receive data stream
12.
DS0 SELECT CONTROL REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3) control the internal RCHBLK and TCHBLK signals respectively. The internal RCHBLK and TCHBLK signals can be used to either control the Hardware Based Signaling attributes of the DS3120 or to decide to which channels the HDLC controller should be mapped.
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RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS (Address=6C to 6E Hex)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 CH9 CH17 RCBR1 (6C) RCBR2 (6D) RCBR3 (6E)
SYMBOLS CH1 - 24
POSITIONS RCBR1.0 - 3.7
NAME AND DESCRIPTION Receive Channel Blocking Control Bits (Signaling Application). 0 = allow the robbed-bit signaling position to be forced to one 1 = do not modify the value in the robbed-bit signaling position Receive Channel Blocking Control Bits (HDLC Application). 0 = do not route the DS0 channel to the HDLC controller 1 = route the DS0 channel to the HDLC controller
TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS (Address=32 to 34 Hex)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 CH9 CH17 TCBR1 (32) TCBR2 (33) TCBR3 (34)
SYMBOLS CH1 - 24
POSITIONS TCBR1.0 - 3.7
NAME AND DESCRIPTION Transmit Channel Blocking Control Bits (Signaling Application). 0 = allow robbed-bit signaling information to be inserted 1 = do not allow robbed-bit signaling information to be inserted Transmit Channel Blocking Control Bits (HDLC Application). 0 = do not source the DS0 channel from the HDLC controller 1 = source the DS0 channel from the HDLC controller
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12.1 RCHBLK & TCHBLK USED FOR SIGNALING CONTROL
On the Receive Side, when Hardware Based Signaling is used, the DS3120 has the ability to force the extracted robbed-bit signaling bit positions to a one. This operation is enabled via the CCR4.5 control bit. When this mode is enabled, the RCHBLK registers can be used to select which DS0 channels should have their robbed-bit signaling bit positions force to one. For the RCHBLK registers to be enabled, the CCR4.6 control bit must be set to one. On the Transmit Side, when Hardware Based Signaling is used, the DS3120 will insert signaling from the TSIG input into the data stream input at TSER. This operation is enabled via the CCR4.2 control bit. When this mode is enabled, the TCHBLK registers can be used to select which DS0 channels should have robbed-bit signaling information inserted and which should not. For the TCHBLK registers to be enabled, the CCR4.1 control bit must be set to one.
12.2 RCHBLK & TCHBLK USED FOR HDLC CONTROL
The RCHBLK and TCHBLK signals can also be used to determine which DS0 channels should be mapped to/from the internal HDLC controller. This function is covered in Section 14.
13.
ELASTIC STORE OPERATION
Each framer in the DS3120 contains dual two-frame (386 bits) elastic stores, one for the receive direction, and one for the transmit direction. These elastic stores are only used when the Interleave Bus Operation Modes (IBO) are enabled (i.e., Modes 9 & 10). When the DS3120 is operated in either of the IBO modes, then the elastic stores must be enabled which means that both the CCR1.7 and CCR1.2 control bits must be set to one. Both elastic stores contain full controlled slip capability and both elastic stores within the framer are fully independent. See Section 18 for a detailed description of the IBO function. Controlled slips in the receive elastic store are reported in the SR1.4 bit and the direction of the slip is reported in the RIR1.3 and RIR1.4 bits. Controlled slips in the transmit elastic store are reported in the RIR2.3 bit and the direction of the slip is reported in the RIR2.5 and RIR2.4 bits. If the receive and transmit clocks of the framers are frequency locked to the 8MCLKI signal, then the elastic stores will never fill or empty and controlled slips will not occur. Two mechanisms are available to the user for resetting the elastic stores. The Elastic Store Reset (TX CCR7.4 & RX - CCR7.5) function forces the elastic stores to a depth of one frame unconditionally. Data is lost during the reset. The second method, the Elastic Store Align (TX - CCR6.5 & RX - CCR6.6) forces the elastic store depth to a minimum depth of half a frame only if the current pointer separation is already less then half a frame. If a realignment occurs data is lost. In both mechanisms, independent resets are provided for both the receive and transmit elastic stores. In most applications, the elastic stores do not need to be reset.
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14.
HDLC CONTROLLER
The DS3120 contains an onboard HDLC controller with 64-byte buffers that can be assigned to either the Facilities Data Link (FDL) or to one or more DS0 channels. If the HDLC controller is assigned to DS0 channels, then it can assigned to any DS0 channel or multiple DS0 channels as well as any specific bits within the DS0 channels. Table 14-1 details how the DS3120 should be configured to select whether the HDLC controller should be assigned to the FDL or to DS0 channels. See Figure 20-5 for details on where the HDLC is placed in the transmit side data flow.
HDLC Assignment Configuration Table 14-1
HDLC Assignment DS0(s) FDL Disable TBOC.6 0 1 0 RDC1.7 / TDC1.7 1 0 0 TCR1.2 1 or 0 1 1 or 0
Note that TBOC.6 = 1 and TDC1.7 = 1 cannot exist without corrupting the data in the FDL (if TCR1.2=1).
14.1 GENERAL OVERVIEW
The DS3120 contains a complete HDLC controller with 64-byte buffers in both the transmit and receive directions as well as separate dedicated hardware for Bit Oriented Codes (BOC). The HDLC controller performs all the necessary overhead for generating and receiving Performance Report Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC controller automatically generates and detects flags, generates and checks the CRC check sum, generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns to the HDLC data stream. The 64-byte buffers in the HDLC controller are large enough to allow a full PRM to be received or transmitted without host intervention. The BOC controller will automatically detect incoming BOC sequences and alert the host. When the BOC ceases, the DS3120 will also alert the host. The user can set the device up to send any of the possible 6-bit BOC codes. There are thirteen registers that the host will use to operate and control the operation of the HDLC and BOC controllers. A brief description of the registers is shown in Table 14-2.
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HDLC/BOC CONTROLLER REGISTER LIST Table 14-2
NAME HDLC Control Register (HCR) HDLC Status Register (HSR) HDLC Interrupt Mask Register (HIMR) Receive HDLC Information Register (RHIR) Receive BOC Register (RBOC) Receive HDLC FIFO Register (RHFR) Receive HDLC DS0 Control Register 1 (RDC1) Receive HDLC DS0 Control Register 2 (RDC2) Transmit HDLC Information Register (THIR) Transmit BOC Register (TBOC) Transmit HDLC FIFO Register (THFR) Transmit HDLC DS0 Control Register 1 (TDC1) Transmit HDLC DS0 Control Register 2 (TDC2) FUNCTION general control over the HDLC and BOC controllers key status information for both transmit and receive directions allows/stops status bits to/from causing an interrupt status information on receive HDLC controller status information on receive BOC controller access to 64-byte HDLC FIFO in receive direction controls the HDLC function when used on DS0 channels status information on transmit HDLC controller enables/disables transmission of BOC codes access to 64-byte HDLC FIFO in transmit direction controls the HDLC function when used on DS0 channels
14.2 STATUS REGISTER FOR THE HDLC
Four of the HDLC/BOC controller registers (HSR, RHIR, RBOC, and THIR) provide status information. When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers will be set to a one. Some of the bits in these four HDLC status registers are latched and some are real time bits that are not latched. Section 14.4 contains register descriptions that list which bits are latched and which are not. With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again. The real time bits report the current instantaneous conditions that are occurring and the history of these bits is not latched. Like the other status registers in the DS3120, the user will always proceed a read of any of the four registers with a write. The byte written to the register will inform the DS3120 which of the latched bits the user wishes to read and have cleared (the real time bits are not affected by writing to the status register). The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is written to a bit location, the read register will be updated with current value and it will be cleared. When a zero is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status and information registers will be immediately followed by a read of the same register. The read result should be logically AND'ed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. This second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. This write-read-write (for polled driven access) or write- read (for interrupt driven access) scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS3120 with higher-order software languages.
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Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware interrupt via the INT* output pin. Each of the events in the HSR can be either masked or unmasked from the interrupt pin via the HDLC Interrupt Mask Register (HIMR). Interrupts will force the INT* pin low when the event occurs. The INT* pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
14.3 BASIC OPERATION DETAILS
To allow the framer to properly source/receive data from/to the HDLC and BOC controller the legacy FDL circuitry (which is described in Section 15) should be disabled and the following bits should be programmed as shown: TCR1.2 = 1 (source FDL data from the HDLC and BOC controller) TBOC.6 = 1 (enable HDLC and BOC controller) CCR2.5 = 0 (disable SLC-96 and D4 Fs-bit insertion) CCR2.4 = 0 (disable legacy FDL zero stuffer) CCR2.1 = 0 (disable SLC-96 reception) CCR2.0 = 0 (disable legacy FDL zero stuffer) IMR2.4 = 0 (disable legacy receive FDL buffer full interrupt) IMR2.3 = 0 (disable legacy transmit FDL buffer empty interrupt) IMR2.2 = 0 (disable legacy FDL match interrupt) IMR2.1 = 0 (disable legacy FDL abort interrupt). As a basic guideline for interpreting and sending both HDLC messages and BOC messages, the following sequences can be applied:
Receive a HDLC Message or a BOC
1. 2. 3. 4. 5. 6. 7. 8. Enable RBOC and RPS interrupts Wait for interrupt to occur If RBOC=1, then follow steps 5 and 6 If RPS=1, then follow steps 7 through 12 If LBD=1, a BOC is present, then read the code from the RBOC register and take action as needed If BD=0, a BOC has ceased, take action as needed and then return to step 1 Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt Read RHIR to obtain REMPTY status a. if REMPTY=0, then record OBYTE, CBYTE, and POK bits and then read the FIFO a1. if CBYTE=0 then skip to step 9 a2. if CBYTE=1 then skip to step 11 b. if REMPTY=1, then skip to step 10 9. Repeat step 8 10. Wait for interrupt, skip to step 8 11. If POK=0, then discard whole packet, if POK=1, accept the packet 12. disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 1.
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Transmit a HDLC Message
1. Make sure HDLC controller is done sending any previous messages and is current sending flags by checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register 2. Enable either the THALF or TNF interrupt 3. Read THIR to obtain TFULL status a. if TFULL=0, then write a byte into the FIFO and skip to next step (special case occurs when the last byte is to be written, in this case set TEOM=1 before writing the byte and then skip to step 6) b. if TFULL=1, then skip to step 5 4. Repeat step 3 5. Wait for interrupt, skip to step 3 6. Disable THALF or TNF interrupt and enable TMEND interrupt 7. Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
Transmit a BOC
1. Write 6-bit code into TBOC 2. Set SBOC bit in TBOC=1
14.4 HDLC/BOC REGISTER DESCRIPTION HCR: HDLC CONTROL REGISTER (Address = 00 Hex)
(MSB) RBR SYMBOL RBR RHR TFS RHR TFS POSITION HCR.7 HCR.6 HCR.5 THR TABT TEOM TZSD (LSB) TCRCD
NAME AND DESCRIPTION Receive BOC Reset. A 0 to 1 transition will reset the BOC circuitry. Must be cleared and set again for a subsequent reset. Receive HDLC Reset. A 0 to 1 transition will reset the HDLC controller. Must be cleared and set again for a subsequent reset. Transmit Flag/Idle Select. 0 = 7Eh 1 = FFh Transmit HDLC/BOC Reset. A 0 to 1 transition will reset both the HDLC controller and the transmit BOC circuitry. Must be cleared and set again for a subsequent reset. Transmit Abort. A 0 to 1 transition will cause the FIFO contents to be dumped and one FEh abort to be sent followed by 7Eh or FFh flags/idle until a new packet is initiated by writing new data into the FIFO. Must be cleared and set again for a subsequent abort to be sent. Transmit End of Message. Should be set to a one just before the last data byte of a HDLC packet is written into the transmit FIFO at THFR. The HDLC controller will clear this bit when the last byte has been transmitted. Transmit Zero Stuffer Defeat. Overrides internal enable. 0 = enable the zero stuffer (normal operation) 1 = disable the zero stuffer
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THR
HCR.4
TABT
HCR.3
TEOM
HCR.2
TZSD
HCR.1
DS3120
SYMBOL TCRCD
POSITION HCR.0
NAME AND DESCRIPTION Transmit CRC Defeat. 0 = enable CRC generation (normal operation) 1 = disable CRC generation
HSR: HDLC STATUS REGISTER (Address = 01 Hex)
(MSB) RBOC SYMBOL RBOC RPE RPS POSITION HSR.7 RHALF RNE THALF TNF (LSB) TMEND
NAME AND DESCRIPTION Receive BOC Detector Change of State. Set whenever the BOC detector sees a change of state from a BOC Detected to a No Valid Code seen or vice versa. The setting of this bit prompt the user to read the RBOC register for details. Receive Packet End. Set when the HDLC controller detects either the finish of a valid message (i.e., CRC check complete) or when the controller has experienced a message fault such as a CRC checking error, or an overrun condition, or an abort has been seen. The setting of this bit prompts the user to read the RHIR register for details. Receive Packet Start. Set when the HDLC controller detects an opening byte. The setting of this bit prompts the user to read the RHIR register for details. Receive FIFO Half Full. Set when the receive 64-byte FIFO fills beyond the half way point. The setting of this bit prompts the user to read the RHIR register for details. Receive FIFO Not Empty. Set when the receive 64-byte FIFO has at least 1 byte available for a read. The setting of this bit prompts the user to read the RHIR register for details. Transmit FIFO Half Empty. Set when the transmit 64-byte FIFO empties beyond the half way point. The setting of this bit prompts the user to read the THIR register for details. Transmit FIFO Not Full. Set when the transmit 64-byte FIFO has at least 1 byte available. The setting of this bit prompts the user to read the THIR register for details. Transmit Message End. Set when the transmit HDLC controller has finished sending a message. The setting of this bit prompts the user to read the THIR register for details.
RPE
HSR.6
RPS
HSR.5
RHALF
HSR.4
RNE
HSR.3
THALF
HSR.2
TNF
HSR.1
TMEND
HSR.0
NOTE:
The RBOC, RPE, RPS, and TMEND bits are latched and will be cleared when read.
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HIMR: HDLC INTERRUPT MASK REGISTER (Address = 02 Hex)
(MSB) RBOC SYMBOL RBOC RPE RPS POSITION HIMR.7 RHALF RNE THALF TNF (LSB) TMEND
NAME AND DESCRIPTION Receive BOC Detector Change of State. 0 = interrupt masked 1 = interrupt enabled Receive Packet End. 0 = interrupt masked 1 = interrupt enabled Receive Packet Start. 0 = interrupt masked 1 = interrupt enabled Receive FIFO Half Full. 0 = interrupt masked 1 = interrupt enabled Receive FIFO Not Empty. 0 = interrupt masked 1 = interrupt enabled Transmit FIFO Half Empty. 0 = interrupt masked 1 = interrupt enabled Transmit FIFO Not Full. 0 = interrupt masked 1 = interrupt enabled Transmit Message End. 0 = interrupt masked 1 = interrupt enabled
RPE
HIMR.6
RPS
HIMR.5
RHALF
HIMR.4
RNE
HIMR.3
THALF
HIMR.2
TNF
HIMR.1
TMEND
HIMR.0
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RHIR: RECEIVE HDLC INFORMATION REGISTER (Address = 03 Hex)
(MSB) RABT SYMBOL RABT RCRCE ROVR RVM REMPTY POK RCRCE ROVR POSITION RHIR.7 RHIR.6 RHIR.5 RHIR.4 RHIR.3 RHIR.2 RVM REMPTY POK CBYTE (LSB) OBYTE
NAME AND DESCRIPTION Abort Sequence Detected. Set whenever the HDLC controller sees 7 or more ones in a row. CRC Error. Set when the CRC checksum is in error. Overrun. Set when the HDLC controller has attempted to write a byte into an already full receive FIFO. Valid Message. Set when the HDLC controller has detected and checked a complete HDLC packet. Empty. A real-time bit that is set high when the receive FIFO is empty. Packet OK. Set when the byte available for reading in the receive FIFO at RHFR is the last byte of a valid message (and hence no abort was seen, no overrun occurred, and the CRC was correct). Closing Byte. Set when the byte available for reading in the receive FIFO at RHFR is the last byte of a message (whether the message was valid or not). Opening Byte. Set when the byte available for reading in the receive FIFO at RHFR is the first byte of a message.
CBYTE
RHIR.1
OBYTE
RHIR.0
NOTE:
The RABT, RCRCE, ROVR, and RVM bits are latched and will be cleared when read.
RBOC: RECEIVE BIT ORIENTED CODE REGISTER (Address = 04 Hex)
(MSB) LBD SYMBOL LBD BD BD BOC5 POSITION RBOC.7 RBOC.6 BOC4 BOC3 BOC2 BOC1 (LSB) BOC0
NAME AND DESCRIPTION Latched BOC Detected. A latched version of the BD status bit (RBOC.6). Will be cleared when read. BOC Detected. A real-time bit that is set high when the BOC detector is presently seeing a valid sequence and set low when no BOC is currently being detected. BOC Bit 5. Last bit received of the 6-bit code word. BOC Bit 4. BOC Bit 3. BOC Bit 2. BOC Bit 1. BOC Bit 0. First bit received of the 6-bit code word.
BOC5 BOC4 BOC3 BOC2 BOC1 BOC0
RBOC.5 RBOC.4 RBOC.3 RBOC.2 RBOC.1 RBOC.0
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NOTE:
1. The LBD bit is latched and will be cleared when read. 2. The RBOC0 to RBOC5 bits display the last valid BOC code verified; these bits will be set to all ones on reset.
RHFR: RECEIVE HDLC FIFO (Address = 05 Hex)
(MSB) HDLC7 SYMBOL HDLC7 HDLC6 HDLC5 HDLC4 HDLC3 HDLC2 HDLC1 HDLC0 HDLC6 HDLC5 POSITION RHFR.7 RHFR.6 RHFR.5 RHFR.4 RHFR.3 RHFR.2 RHFR.1 RHFR.0 HDLC4 HDLC3 HDLC2 HDLC1 (LSB) HDLC0
NAME AND DESCRIPTION HDLC Data Bit 7. MSB of a HDLC packet data byte. HDLC Data Bit 6. HDLC Data Bit 5. HDLC Data Bit 4. HDLC Data Bit 3. HDLC Data Bit 2. HDLC Data Bit 1. HDLC Data Bit 0. LSB of a HDLC packet data byte.
THIR: TRANSMIT HDLC INFORMATION (Address = 06 Hex)
(MSB) - SYMBOL - - - - - TEMPTY TFULL UDR - - POSITION THIR.7 THIR.6 THIR.5 THIR.4 THIR.3 THIR.2 THIR.1 THIR.0 - - TEMPTY TFULL (LSB) UDR
NAME AND DESCRIPTION Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Transmit FIFO Empty. A real-time bit that is set high when the FIFO is empty. Transmit FIFO Full. A real-time bit that is set high when the FIFO is full. Underrun. Set when the transmit FIFO unwantedly empties out and an abort is automatically sent.
NOTE:
The UDR bit is latched and will be cleared when read.
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TBOC: TRANSMIT BIT ORIENTED CODE (Address = 07 Hex)
(MSB) SBOC SYMBOL SBOC HBEN BOC5 POSITION TBOC.7 BOC4 BOC3 BOC2 BOC1 (LSB) BOC0
NAME AND DESCRIPTION Send BOC. Rising edge triggered. Must be transitioned from a 0 to a 1 transmit the BOC code placed in the BOC0 to BOC5 bits instead of data from the HDLC controller. Transmit HDLC & BOC Controller Enable. 0 = source FDL data from the TLINK pin 1 = source FDL data from the onboard HDLC and BOC controller BOC Bit 5. Last bit transmitted of the 6-bit code word. BOC Bit 4. BOC Bit 3. BOC Bit 2. BOC Bit 1. BOC Bit 0. First bit transmitted of the 6-bit code word.
HBEN
TBOC.6
BOC5 BOC4 BOC3 BOC2 BOC1 BOC0
TBOC.5 TBOC.4 TBOC.3 TBOC.2 TBOC.1 TBOC.0
THFR: TRANSMIT HDLC FIFO (Address = 08 Hex)
(MSB) HDLC7 SYMBOL HDLC7 HDLC6 HDLC5 HDLC4 HDLC3 HDLC2 HDLC1 HDLC0 HDLC6 HDLC5 POSITION THFR.7 THFR.6 THFR.5 THFR.4 THFR.3 THFR.2 THFR.1 THFR.0 HDLC4 HDLC3 HDLC2 HDLC1 (LSB) HDLC0
NAME AND DESCRIPTION HDLC Data Bit 7. MSB of a HDLC packet data byte. HDLC Data Bit 6. HDLC Data Bit 5. HDLC Data Bit 4. HDLC Data Bit 3. HDLC Data Bit 2. HDLC Data Bit 1. HDLC Data Bit 0. LSB of a HDLC packet data byte.
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RDC1: RECEIVE HDLC DS0 CONTROL REGISTER 1 (Address = 90 Hex)
(MSB) RDS0E SYMBOL RDS0E RDS0M POSITION RDC1.7 RD4 RD3 RD2 RD1 (LSB) RD0
NAME AND DESCRIPTION HDLC DS0 Enable. 0 = use receive HDLC controller for the FDL. 1 = use receive HDLC controller for one or more DS0 channels. Not Assigned. Should be set to 0. DS0 Selection Mode. 0 = utilize the RD0 to RD4 bits to select which single DS0 channel to use. 1 = utilize the RCHBLK control registers to select which DS0 channels to use. See Section 12. DS0 Channel Select Bit 4. MSB of the DS0 channel select. DS0 Channel Select Bit 3. DS0 Channel Select Bit 2. DS0 Channel Select Bit 1. DS0 Channel Select Bit 0. LSB of the DS0 channel select.
RDS0M
RDC1.6 RDC1.5
RD4 RD3 RD2 RD1 RD0
RDC1.4 RDC1.3 RDC1.2 RDC1.1 RDC1.0
RDC2: RECEIVE HDLC DS0 CONTROL REGISTER 2 (Address = 91 Hex)
(MSB) RDB8 SYMBOL RDB8 RDB7 RDB6 RDB5 RDB4 RDB3 RDB2 RDB1 RDB7 RDB6 POSITION RDC2.7 RDC2.6 RDC2.5 RDC2.4 RDC2.3 RDC2.2 RDC2.1 RDC2.0 RDB5 RDB4 RDB3 RDB2 (LSB) RDB1
NAME AND DESCRIPTION DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to stop this bit from being used. DS0 Bit 7 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 6 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 5 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 4 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 3 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 2 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to stop this bit from being used.
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TDC1: TRANSMIT HDLC DS0 CONTROL REGISTER 1 (Address = 92 Hex)
(MSB) TDS0E SYMBOL TDS0E TDS0M POSITION TDC1.7 TD4 TD3 TD2 TD1 (LSB) TD0
NAME AND DESCRIPTION HDLC DS0 Enable. 0 = use transmit HDLC controller for the FDL. 1 = use transmit HDLC controller for one or more DS0 channels. Not Assigned. Should be set to 0. DS0 Selection Mode. 0 = utilize the TD0 to TD4 bits to select which single DS0 channel to use. 1 = utilize the TCHBLK control registers to select which DS0 channels to use. See Section 12. DS0 Channel Select Bit 4. MSB of the DS0 channel select. DS0 Channel Select Bit 3. DS0 Channel Select Bit 2. DS0 Channel Select Bit 1. DS0 Channel Select Bit 0. LSB of the DS0 channel select.
TDS0M
TDC1.6 TDC1.5
TD4 TD3 TD2 TD1 TD0
TDC1.4 TDC1.3 TDC1.2 TDC1.1 TDC1.0
TDC2: TRANSMIT HDLC DS0 CONTROL REGISTER 2 (Address = 93 Hex)
(MSB) TDB8 SYMBOL TDB8 TDB7 TDB6 TDB5 TDB4 TDB3 TDB2 TDB1 TDB7 TDB6 POSITION TDC2.7 TDC2.6 TDC2.5 TDC2.4 TDC2.3 TDC2.2 TDC2.1 TDC2.0 TDB5 TDB4 TDB3 TDB2 (LSB) TDB1
NAME AND DESCRIPTION DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to stop this bit from being used. DS0 Bit 7 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 6 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 5 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 4 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 3 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 2 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to stop this bit from being used.
15.
LEGACY FDL SUPPORT & D4/SLC-96 SUPPORT
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15.1 OVERVIEW
The DS3120 maintains the circuitry that existed in previous generations of Dallas Semiconductor's framers. Sections 15.2 & 15.3 cover the circuitry and operation of this legacy functionality. In new applications, it is recommended that the HDLC controller and BOC controller described in Section 14 be used. It is possible to have both the new HDLC/BOC controller and the legacy hardware working at the same time.
15.2 RECEIVE SECTION
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 times 250 us). The framer will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via IMR2.4, the INT* pin will toggle low indicating that the buffer has filled and needs to be read. The user has 2 ms to read this data before it is lost. If the byte in the RFDL matches either of the bytes programmed into the RMTCH1 or RMTCH2 registers, then the SR2.2 bit will be set to a one and the INT* pin will toggled low if enabled via IMR2.2. This feature allows an external microcontroller to ignore the FDL or Fs pattern until an important event occurs. The framer also contains a zero destuffer, which is controlled via the CCR2.0 bit. In both ANSI T1.403 and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no more than 5 ones should be transmitted in a row so that the data does not resemble an opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS3120 will automatically look for 5 ones in a row, followed by a zero. If it finds such a pattern, it will automatically remove the zero. If the zero destuffer sees six or more ones in a row followed by a zero, the zero is not removed. The CCR2.0 bit should always be set to a one when the DS3120 is extracting the FDL.
RFDL: RECEIVE FDL REGISTER (Address = 28 Hex)
(MSB) RFDL7 SYMBOL RFDL7 RFDL0 RFDL6 RFDL5 POSITION RFDL.7 RFDL.0 RFDL4 RFDL3 RFDL2 RFDL1 (LSB) RFDL0
NAME AND DESCRIPTION MSB of the Received FDL Code LSB of the Received FDL Code
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs bits. The LSB is received first.
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RMTCH1: RECEIVE FDL MATCH REGISTER 1 (Address = 29 Hex) RMTCH2: RECEIVE FDL MATCH REGISTER 2 (Address = 2A Hex)
(MSB) RMFDL7 RMFDL6 RMFDL5 RMFDL4 RMFDL3 RMFDL2 RMFDL1 (LSB) RMFDL0
SYMBOL RMFDL7 RMFDL0
POSITION RMTCH1.7 RMTCH2.7 RMTCH1.0 RMTCH2.0
NAME AND DESCRIPTION MSB of the FDL Match Code LSB of the FDL Match Code
When the byte in the Receive FDL Register matches either of the two Receive FDL Match Registers (RMTCH1/RMTCH2), SR2.2 will be set to a one and the INT* will go active if enabled via IMR2.2.
15.3 TRANSMIT SECTION
The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing T1 data stream. After the full 8 bits has been shifted out, the framer will signal the host microcontroller that the buffer is empty and that more data is needed by setting the SR2.3 bit to a one. The INT* will also toggle low if enabled via IMR2.3. The user has 2 ms to update the TFDL with a new value. If the TFDL is not updated, the old value in the TFDL will be transmitted once again. The framer also contains a zero stuffer, which is controlled via the CCR2.4 bit. In both ANSI T1.403 and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no more than 5 ones should be transmitted in a row so that the data does not resemble an opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the framer will automatically look for 5 ones in a row. If it finds such a pattern, it will automatically insert a zero after the five ones. The CCR2.0 bit should always be set to a one when the framer is inserting the FDL.
TFDL: TRANSMIT FDL REGISTER (Address = 7E Hex)
[Also used to insert Fs framing pattern in D4 framing mode; see Section 15.4] (MSB) TFDL7 SYMBOL TFDL7 TFDL0 (LSB) TFDL0
TFDL6
TFDL5 POSITION TFDL.7 TFDL.0
TFDL4
TFDL3
TFDL2
TFDL1
NAME AND DESCRIPTION MSB of the FDL code to be transmitted LSB of the FDL code to be transmitted
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first.
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15.4 D4/SLC-96 OPERATION
In the D4 framing mode, the framer uses the TFDL register to insert the Fs framing pattern. To allow the device to properly insert the Fs framing pattern, the TFDL register at address 7Eh must be programmed to 1Ch and the following bits must be programmed as shown: TCR1.2=0 (source Fs data from the TFDL register) CCR2.5=1 (allow the TFDL register to load on multiframe boundaries). Since the SLC-96 message fields share the Fs-bit position, the user can access the these message fields via the TFDL and RFDL registers.
16.
PROGRAMMABLE IN-BAND CODE GENERATION AND DETECTION
Each framer in the DS3120 has the ability to generate and detect a repeating bit pattern that is from one to 8 bits in length. To transmit a pattern, the user will load the pattern to be sent into the Transmit Code Definition (TCD) register and select the proper length of the pattern by setting the TC0 and TC1 bits in the In-Band Code Control (IBCC) register. Once this is accomplished, the pattern will be transmitted as long as the TLOOP control bit (CCR3.1) is enabled. Normally (unless the transmit formatter is programmed to not insert the F-bit position) the framer will overwrite the repeating pattern once every 193 bits to allow the F-bit position to be sent. See Figure 20-5 for more details. As an example, if the user wished to transmit the standard "loop up" code for Channel Service Units which is a repeating pattern of ...10000100001... then 80h would be loaded into TDR and the length would set to 5 bits. Each framer can detect two separate repeating patterns to allow for both a "loop up" code and a "loop down" code to be detected. The user will program the codes to be detected in the Receive Up Code Definition (RUPCD) register and the Receive Down Code Definition (RDNCD) register and the length of each pattern will be selected via the IBCC register. The framer will detect repeating pattern codes in both framed and unframed circumstances with bit error rates as high as 10**-2. The code detector has a nominal integration period of 48 ms. Hence, after about 48 ms of receiving either code, the proper status bit (LUP at SR1.7 and LDN at SR1.6) will be set to a one. Normally codes are sent for a period of 5 seconds. It is recommend that the software poll the framer every 100 ms to 1000 ms until 5 seconds has elapsed to insure that the code is continuously present.
IBCC: IN-BAND CODE CONTROL REGISTER (Address=12 Hex)
(MSB) TC1 SYMBOL TC1 TC0 RUP2 RUP1 RUP0 RDN2 RDN1 RDN0 TC0 RUP2 POSITION IBCC.7 IBCC.6 IBCC.5 IBCC.4 IBCC.3 IBCC.2 IBCC.1 IBCC.0 RUP1 RUP0 RDN2 RDN1 (LSB) RDN0
NAME AND DESCRIPTION Transmit Code Length Definition Bit 1. See Table 16-1 Transmit Code Length Definition Bit 0. See Table 16-1 Receive Up Code Length Definition Bit 2. See Table 16-2 Receive Up Code Length Definition Bit 1. See Table 16-2 Receive Up Code Length Definition Bit 0. See Table 16-2 Receive Down Code Length Definition Bit 2. See Table 16-2 Receive Down Code Length Definition Bit 1. See Table 16-2 Receive Down Code Length Definition Bit 0. See Table 16-2
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TRANSMIT CODE LENGTH Table 16-1
TC1 0 0 1 1 TC0 0 1 0 1 LENGTH SELECTED 5 bits 6 bits / 3 bits 7 bits 8 bits / 4 bits / 2 bits / 1 bits
RECEIVE CODE LENGTH Table 16-2
RUP2/ RDN2 0 0 0 0 1 1 1 1 RUP1/ RDN1 0 0 1 1 0 0 1 1 RUP0/ RDN0 0 1 0 1 0 1 0 1 LENGTH SELECTED 1 bits 2 bits 3 bits 4 bits 5 bits 6 bits 7 bits 8 bits
TCD: TRANSMIT CODE DEFINITION REGISTER (Address=13 Hex)
(MSB) C7 SYMBOL C7 C6 C5 C4 C3 C2 C1 C0 C6 C5 POSITION TCD.7 TCD.6 TCD.5 TCD.4 TCD.3 TCD.2 TCD.1 TCD.0 C4 C3 C2 C1 (LSB) C0
NAME AND DESCRIPTION Transmit Code Definition Bit 7. pattern. Transmit Code Definition Bit 6. Transmit Code Definition Bit 5. Transmit Code Definition Bit 4. Transmit Code Definition Bit 3. Transmit Code Definition Bit 2. length is selected. Transmit Code Definition Bit 1. length is selected. Transmit Code Definition Bit 0. bit length is selected. First bit of the repeating
A Don't Care if a 5 bit A Don't Care if a 5 or 6 bit A Don't Care if a 5, 6 or 7
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RUPCD: RECEIVE UP CODE DEFINITION REGISTER (Address=14 Hex)
(MSB) C7 SYMBOL C7 C6 C5 C4 C3 C2 C1 C0 C6 C5 POSITION RUPCD.7 RUPCD.6 RUPCD.5 RUPCD.4 RUPCD.3 RUPCD.2 RUPCD.1 RUPCD.0 C4 C3 C2 C1 (LSB) C0
NAME AND DESCRIPTION Receive Up Code Definition Bit 7. First bit of the repeating pattern. Receive Up Code Definition Bit 6. A Don't Care if a 1 bit length is selected. Receive Up Code Definition Bit 5. A Don't Care if a 1 or 2 bit length is selected. Receive Up Code Definition Bit 4. A Don't Care if a 1 to 3 bit length is selected. Receive Up Code Definition Bit 3. A Don't Care if a 1 to 4 bit length is selected. Receive Up Code Definition Bit 2. A Don't Care if a 1 to 5 bit length is selected. Receive Up Code Definition Bit 1. A Don't Care if a 1 to 6 bit length is selected. Receive Up Code Definition Bit 0. A Don't Care if a 1 to 7 bit length is selected.
RDNCD: RECEIVE DOWN CODE DEFINITION REGISTER (Address=15 Hex)
(MSB) C7 SYMBOL C7 C6 C5 C4 C3 C2 C1 C0 C6 C5 POSITION RDNCD.7 RDNCD.6 RDNCD.5 RDNCD.4 RDNCD.3 RDNCD.2 RDNCD.1 RDNCD.0 C4 C3 C2 C1 (LSB) C0
NAME AND DESCRIPTION Receive Down Code Definition Bit 7. pattern. Receive Down Code Definition Bit 6. length is selected. Receive Down Code Definition Bit 5. bit length is selected. Receive Down Code Definition Bit 4. bit length is selected. Receive Down Code Definition Bit 3. bit length is selected. Receive Down Code Definition Bit 2. bit length is selected. Receive Down Code Definition Bit 1. bit length is selected. Receive Down Code Definition Bit 0. bit length is selected. First bit of the repeating A Don't Care if a 1 bit A Don't Care if a 1 or 2 A Don't Care if a 1 to 3 A Don't Care if a 1 to 4 A Don't Care if a 1 to 5 A Don't Care if a 1 to 6 A Don't Care if a 1 to 7
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17.
TRANSMIT TRANSPARENCY
Each of the 24 T1 channels in the transmit direction of the framer can be either forced to be transparent or in other words, can be forced to stop Bit 7 Stuffing and/or Processor Based Robbed Signaling from overwriting the data in the channels. Transparency can be invoked on a channel by channel basis by properly setting the TTR1, TTR2, and TTR3 registers.
TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTER (Address=39 to 3B Hex)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 CH9 CH17 TTR1 (39) TTR2 (3A) TTR3 (3B)
SYMBOLS CH1-24
POSITIONS TTR1.0-3.7
NAME AND DESCRIPTION Transmit Transparency Registers. 0 = this DS0 channel is not transparent 1 = this DS0 channel is transparent
Each of the bit position in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represent a DS0 channel in the outgoing frame. When these bits are set to a one, the corresponding channel is transparent (or clear). If a DS0 is programmed to be clear, no robbed bit signaling will be inserted nor will the channel have Bit 7 stuffing performed. However, in the D4 framing mode, Bit 2 will be overwritten by a zero when a Yellow Alarm is transmitted. Also the user has the option to prevent the TTR registers from determining which channels are to have Bit 7 stuffing performed. If the TCR2.0 and TCR1.3 bits are set to one, then all 24 T1 channels will have Bit 7 stuffing performed on them regardless of how the TTR registers are programmed. In this manner, the TTR registers are only affecting which channels are to have robbed bit signaling inserted into them. See Figure 20-5 for more details.
18.
8 MHZ INTERLEAVED BUS OPERATION (IBO)
The DS3120 has the ability to aggregate four T1 datastreams into a single 8.192 MHz datastream. This functionality is called Interleaved Bus Operation (IBO) and it is available in Modes 9 & 10. See Section 3 for a discussion of the various modes within the device. The DS3120 can also support the aggregation of just two T1 datastreams into a single 4.096 MHz datastream but this functionality is not covered in this data sheet. Please contact the factory for support on 4.096 MHz applications. In IBO operation, the device must be supplied a 8 MHz clock and frame sync via the 8MCLKI and 8MSYNC inputs respectively and the elastic stores must be enabled via the TESE and RESE control bits in the CCR1 register (see Section 6). The clock and sync signals might be independently generated or they might be sourced from the 8MCLKO and CTSYNC outputs. The 28 T1 framers within the DS3120 are combined into seven groups of four framers each as shown below in Table 18-1 and in Figure 18-1. Within each IBO group, the four T1 datastreams can be either frame interleaved or byte interleaved. This selection is made via the INTSEL control bit in the IBO register. It is acceptable to have some IBO groups using frame interleaving and the others using byte interleaving. If the application requires frame interleaving, then the 8MCLKI clock must be frequency locked to RCLK (i.e., frame slips cannot occur). This restriction does not apply to byte interleaved applications (i.e., frame slips can occur).
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IBO Group Assignment Table 18-1
IBO Group Number 1 2 3 4 5 6 7 Framers in the Group 1/2/3/4 5/6/7/8 9 / 10 / 11 / 12 13 / 14 / 15 / 16 17 / 18 / 19 / 20 21 / 22 / 23 / 24 25 / 26 / 27 / 28
The 8 MHz IBO bus contains 128 DS0 channels. Depending on whether the application is running byte interleaved or frame interleaved, the DS3120 will map the 24 channels of each of the four T1 frames into the 128 DS0 channels as shown in Table 18-2. The fourth channel from each framer will be forced to one. The F-bit will be passed through the device in the MSB of the first channel out of the device. Via TCR1.6, the MSB of the first channel can be sampled as the F-bit.
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8 MHz INTERLEAVED BUS OPERATION EXTERNAL PIN CONNECTION Figure 18-1
optional connections CTSYNC 8MCLKO 8MCLKI 8MSYNC RSER1 RSER2 RSER3 RSER4 RSIG1 RSIG2 RSIG3 RSIG4 TSER1 TSER2 TSER3 TSER4 TSIG1 TSIG2 TSIG3 TSIG4 RSER5 RSER6 RSER7 RSER8 RSIG5 RSIG6 RSIG7 RSIG8 TSER5 TSER6 TSER7 TSER8 TSIG5 TSIG6 TSIG7 TSIG8 8KHz Frame Sync 8MHz Clock 8MHz Clock 8KHz Frame Sync
IBO Group #1
DS3120
IBO Group #2
RSER25 RSER26 RSER27 RSER28 RSIG25 RSIG26 RSIG27 RSIG28 TSER25 TSER26 TSER27 TSER28 TSIG25 TSIG26 TSIG27 TSIG28
IBO Group #7
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8 MHz IBO CHANNEL ASSIGNMENT Table 18-2
IBO Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Byte Interleaved Channel Assignment (only IBO Group #1 is listed) Blank Channel (MSB contains the F Bit) Blank Channel (MSB contains the F Bit) Blank Channel (MSB contains the F Bit) Blank Channel (MSB contains the F Bit) Framer 1 / T1 Channel 1 Framer 2 / T1 Channel 1 Framer 3 / T1 Channel 1 Framer 4 / T1 Channel 1 Framer 1 / T1 Channel 2 Framer 2 / T1 Channel 2 Framer 3 / T1 Channel 2 Framer 4 / T1 Channel 2 Framer 1 / T1 Channel 3 Framer 2 / T1 Channel 3 Framer 3 / T1 Channel 3 Framer 4 / T1 Channel 3 Blank Channel Blank Channel Blank Channel Blank Channel Framer 1 / T1 Channel 4 Framer 2 / T1 Channel 4 Framer 3 / T1 Channel 4 Framer 4 / T1 Channel 4 Framer 1 / T1 Channel 5 Framer 2 / T1 Channel 5 Framer 3 / T1 Channel 5 Framer 4 / T1 Channel 5 Framer 1 / T1 Channel 6 Framer 2 / T1 Channel 6 Framer 3 / T1 Channel 6 Framer 4 / T1 Channel 6 Blank Channel Blank Channel Blank Channel Blank Channel Framer 1 / T1 Channel 7 Framer 2 / T1 Channel 7 Frame Interleaved Channel Assignment (only IBO Group #1 is listed) Blank Channel (MSB contains the F Bit) Framer 1 / T1 Channel 1 Framer 1 / T1 Channel 2 Framer 1 / T1 Channel 3 Blank Channel Framer 1 / T1 Channel 4 Framer 1 / T1 Channel 5 Framer 1 / T1 Channel 6 Blank Channel Framer 1 / T1 Channel 7 Framer 1 / T1 Channel 8 Framer 1 / T1 Channel 9 Blank Channel Framer 1 / T1 Channel 10 Framer 1 / T1 Channel 11 Framer 1 / T1 Channel 12 Blank Channel Framer 1 / T1 Channel 13 Framer 1 / T1 Channel 14 Framer 1 / T1 Channel 15 Blank Channel Framer 1 / T1 Channel 16 Framer 1 / T1 Channel 17 Framer 1 / T1 Channel 18 Blank Channel Framer 1 / T1 Channel 19 Framer 1 / T1 Channel 20 Framer 1 / T1 Channel 21 Blank Channel Framer 1 / T1 Channel 22 Framer 1 / T1 Channel 23 Framer 1 / T1 Channel 24 Blank Channel (MSB contains the F Bit) Framer 2 / T1 Channel 1 Framer 2 / T1 Channel 2 Framer 2 / T1 Channel 3 Blank Channel Framer 2 / T1 Channel 4
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IBO Channel Number 123 124 125 126 127 128
Byte Interleaved Channel Assignment (only IBO Group #1 is listed) Framer 3 / T1 Channel 23 Framer 4 / T1 Channel 23 Framer 1 / T1 Channel 24 Framer 2 / T1 Channel 24 Framer 3 / T1 Channel 24 Framer 4 / T1 Channel 24
Frame Interleaved Channel Assignment (only IBO Group #1 is listed) Framer 4 / T1 Channel 20 Framer 4 / T1 Channel 21 Blank Channel Framer 4 / T1 Channel 22 Framer 4 / T1 Channel 23 Framer 4 / T1 Channel 24
IBO: INTERLEAVE BUS OPERATION REGISTER (Address = 94 Hex)
(MSB) SYMBOL IBOEN POSITION IBO.6 IBO.6 IBO.5 IBO.4 IBO.3 IBOEN INTSEL MSEL0 (LSB) MSEL1
NAME AND DESCRIPTION Not Assigned. Should be set to 0. Not Assigned. Should be set to 0. Not Assigned. Should be set to 0. Not Assigned. Should be set to 0. Interleave Bus Operation Enable. This bit should be set to one in Modes 9 & 10. Set to zero in all other Modes. 0 = Interleave Bus Operation disabled. 1 = Interleave Bus Operation enabled. Interleave Type Select. 0 = Byte interleave. 1 = Frame interleave. Master Device Bus Select Bit 0. Should be set to zero. Master Device Bus Select Bit 1. Should be set to zero on framers 2 / 3 / 4 / 6 / 7 / 8 / 10 / 11 / 12 / 14 / 15 / 16 / 18 / 19 / 20 / 22 / 23 / 24 / 26 / 27 / 28. Should be set to one on framers 1 / 5 / 9 / 13 / 17 / 21 / 25.
INTSEL
IBO.2
MSEL0 MSEL1
IBO.1 IBO.0
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8 MHz INTERLEAVED BUS OPERATION TIMING (BYTE INTERLEAVING) Figure 18-2
(only IBO Group #1 is shown; other IBO Groups operate in a similar fashion)
8MSYNC
CHANNEL #
127
128
1
2
3
4
5
6
7
8
RSER
FR3 CH24 FR4 CH24 F
F
F
F
FR1 CH1
FR2 CH1
FR3 CH1
FR4 CH1
TSER(1)
FR3 CH24 FR4 CH24 F
F
F
F
FR1 CH1
FR2 CH1
FR3 CH1
FR4 CH1
RSIG(2)
FR3 CH24 FR4 CH24
FR1 CH1
FR2 CH1
FR3 CH1
FR4 CH1
TSIG(3)
FR3 CH24 FR4 CH24
FR1 CH1
FR2 CH1
FR3 CH1
FR4 CH1
8 MHz INTERLEAVED BUS OPERATION TIMING (FRAME INTERLEAVING) Figure 18-3
(only IBO Group #1 is shown; other IBO Groups operate in a similar fashion)
8MSYNC
CHANNEL #
127
128
1
2
3
4
5
6
7
8
RSER
FR4 CH23 FR4 CH24 F
FR1 CH1
FR1 CH2
FR1 CH3
FR1 CH4
FR1 CH5
FR1 CH6
TSER
FR4 CH23 FR4 CH24 F
FR1 CH1
FR1 CH2
FR1 CH3
FR1 CH4
FR1 CH5
FR1 CH6
RSIG
FR4 CH23 FR4 CH24
FR1 CH1
FR1 CH2
FR1 CH3
FR1 CH4
FR1 CH5
FR1 CH6
TSIG
FR4 CH23 FR4 CH24
FR1 CH1
FR1 CH2
FR1 CH3
FR1 CH4
FR1 CH5
FR1 CH6
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19.
JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
19.1 DESCRIPTION
The DS3120 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included with this design are HIGHZ, CLAMP, and IDCODE. See Figure 19-1 for a block diagram. The DS3120 contains the following items, which meet the requirements, set by the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Test Access Port (TAP) TAP Controller Instruction Register Bypass Register Boundary Scan Register Device Identification Register Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994. The Test Access Port has the necessary interface pins; JTRST*, JTCLK, JTMS, JTDI, and JTDO. See the signal descriptions for details.
BOUNDARY SCAN ARCHITECTURE Figure 19-1
Boundary Scan Register Identification Register Bypass Register
MUX
Instruction Register
Test Access Port Controller
+V 10K 10K +V 10K +V
Select Output Enable
JTDI
JTMS
JTCLK
JTRST
JTDO
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19.2 TAP CONTROLLER STATE MACHINE
This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. Please see Figure 19.2 for details on each of the states described below.
TAP Controller
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK.
Test-Logic-Reset
Upon power up of the DS3120, the TAP Controller will be in the Test-Logic-Reset state. The Instruction register will contain the IDCODE instruction. All system logic of the DS3120 will operate normally.
Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and Test registers will remain idle.
Select-DR-Scan
All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the controller into the Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the controller to the Select-IR
Capture-DR
Data may be parallel-loaded into the Test Data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the Test register will remain at its current value. On the rising edge of JTCLK, the controller will go to the ShiftDR state if JTMS is low or it will go to the Exit1-DR state if JTMS is high.
Shift-DR
The Test Data register selected by the current instruction will be connected between JTDI and JTDO and will shift data one stage towards its serial output on each rising edge of JTCLK. If a Test Register selected by the current instruction is not placed in the serial path, it will maintain its previous state.
Exit1-DR
While in this state, a rising edge on JTCLK with JTMS high will put the controller in the Update-DR state, and terminate the scanning process. A rising edge on JTCLK with JTMS low will put the controller in the Pause-DR state.
Pause-DR
Shifting of the test registers is halted while in this state. All Test registers selected by the current instruction will retain their previous state. The controller will remain in this state while JTMS is low. A rising edge on JTCLK with JTMS high will put the controller in the Exit2-DR state.
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Exit2-DR
While in this state, a rising edge on JTCLK with JTMS high will put the controller in the Update-DR state and terminate the scanning process. A rising edge on JTCLK with JTMS low will enter the Shift-DR state.
Update-DR
A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of the Test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register. A rising edge on JTCLK with JTMS low, will put the controller in the Run-Test-Idle state. With JTMS high, the controller will enter the Select-DR-Scan state.
Select-IR-Scan
All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS low, a rising edge of JTCLK moves the controller into the Capture-IR state and will initiate a scan sequence for the Instruction register. JTMS high during a rising edge on JTCLK puts the controller back into the Test-Logic-Reset state.
Capture-IR
The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is high on the rising edge of JTCLK, the controller will enter the Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller will enter the Shift-IR state.
Shift-IR
In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one stage for every rising edge of JTCLK towards the serial output. The parallel registers, as well as all Test registers remain at their previous states. A rising edge on JTCLK with JTMS high will move the controller to the Exit1-IR state. A rising edge on JTCLK with JTMS low will keep the controller in the Shift-IR state while moving data one stage thorough the instruction shift register.
Exit1-IR
A rising edge on JTCLK with JTMS low will put the controller in the Pause-IR state. If JTMS is high on the rising edge of JTCLK, the controller will enter the Update-IR state and terminate the scanning process.
Pause-IR
Shifting of the instruction shift register is halted temporarily. With JTMS high, a rising edge on JTCLK will put the controller in the Exit2-IR state. The controller will remain in the Pause-IR state if JTMS is low during a rising edge on JTCLK.
Exit2-IR
A rising edge on JTCLK with JTMS low will put the controller in the Update-IR state. The controller will loop back to Shift-IR if JTMS is high during a rising edge of JTCLK in this state.
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Update-IR
The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on JTCLK with JTMS low, will put the controller in the Run-Test-Idle state. With JTMS high, the controller will enter the Select-DR-Scan state.
TAP Controller State Machine Figure 19-2
1 Test Logic Reset 0 Run Test/ Idle
0
1
Select DR-Scan 0 1 Capture DR 0 Shift DR 1 Exit DR 0 Pause DR 1 0 Exit2 DR 1 Update DR 1 0
1
Select IR-Scan 0 1 Capture IR 0
1
0 1
Shift IR 1 Exit IR 0
0 1
0 0
Pause IR 1 Exit2 IR 1 Update IR 1 0
0
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19.3 INSTRUCTION REGISTER AND INSTRUCTIONS
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS low will shift the data one stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS high will move the controller to the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions supported by the DS3120 with their respective operational binary codes are shown in Table 19-1.
Instruction Codes Table 19-1
Instruction SAMPLE/PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE Selected Register Boundary Scan Bypass Boundary Scan Boundary Scan Boundary Scan Device Identification Instruction Codes 010 111 000 011 100 001
SAMPLE/PRELOAD
A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The digital I/Os of the DS3120 can be sampled at the boundary scan register without interfering with the normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the DS3120 to shift data into the boundary scan register via JTDI using the Shift-DR state.
EXTEST
EXTEST allows testing of all interconnections to the DS3120. When the EXTEST instruction is latched in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output pins will be driven. The boundary scan register will be connected between JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the device's normal operation.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the Identification Test register is selected. The device identification code will be loaded into the Identification register on the rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register's parallel output. The ID code will always have a `1' in the LSB position. The next 11 bits identify the manufacturer's JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. The device ID code for the DS3120 is 0000C143h.
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HIGHZ
All digital outputs of the DS3120 will be placed in a high impedance state. The BYPASS register will be connected between JTDI and JTDO.
CLAMP
All digital outputs of the DS3120 will output data from the boundary scan parallel output while connecting the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
19.4 TEST REGISTERS
IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. An optional test register has been included with the DS3120 design. This test register is the identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells and is 321 bits in length. Table 19-2 shows all of the cell bit locations and definitions.
Bypass Register
This is a single 1-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions, which provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-LogicReset state.
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BOUNDARY SCAN REGISTER DESCRIPTION Table 19-2
Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Symbol MODE0 MODE1 MODE2 MODE3 RNRZ28 RCLK28 TNRZ28 RNRZ27 RCLK27 TNRZ27 RNRZ26 RCLK26 TNRZ26 RNRZ25 RCLK25 TNRZ25 RNRZ24 RCLK24 TNRZ24 RNRZ23 RCLK23 TNRZ23 RNRZ22 RCLK22 TNRZ22 RNRZ21 RCLK21 TNRZ21 RNRZ20 RCLK20 TNRZ20 RNRZ19 RCLK19 TNRZ19 RNRZ18 RCLK18 TNRZ18 RNRZ17 RCLK17 TNRZ17 RNRZ16 RCLK16 TNRZ16 RNRZ15 Lead C2 E4 E3 D2 C1 F3 F4 E2 D1 F2 G5 G4 G3 E1 F1 G2 H4 H5 H3 G1 H2 J3 J4 J5 J2 J1 K1 K3 K4 K5 K2 L1 M1 L2 L3 L4 L5 M2 N1 M3 N2 M5 M4 P1
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I/O or Control Bit Description I I I I I I O I I O I I O I I O I I O I I O I I O I I O I I O I I O I I O I I O I I O I
DS3120
Bit 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
Symbol RCLK15 TNRZ15 RNRZ14 RCLK14 TNRZ14 RNRZ13 RCLK13 TNRZ13 RNRZ12 RCLK12 TNRZ12 RNRZ11 RCLK11 TNRZ11 RNRZ10 RCLK10 TNRZ10 RNRZ9 RCLK9 TNRZ9 RNRZ8 RCLK8 TNRZ8 RNRZ7 RCLK7 TNRZ7 RNRZ6 RCLK6 TNRZ6 RNRZ5 RCLK5 TNRZ5 RNRZ4 RCLK4 TNRZ4 RNRZ3 RCLK3 TNRZ3 RNRZ2 RCLK2 TNRZ2 RNRZ1 RCLK1 TNRZ1 RSYNC28 RSER28
Lead N3 R1 P2 N5 N4 T1 P3 R2 P5 P4 T2 R3 V1 W1 Y1 R4 U2 T3 V2 W2 T4 U3 V3 U5 V5 W4 Y2 Y3 U6 T7 V6 W5 Y4 U7 W6 V7 Y5 W7 U8 T8 Y6 V8 Y7 W8 U9 T9
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I/O or Control Bit Description I O I I O I I O I I O I I O I I O I I O I I O I I O I I O I I O I I O I I O I I O I I O O O
DS3120
Bit 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121
Symbol TCLK28/RSIG28.cntl TCLK28/RSIG28 TSER28 TSYNC28/TSIG28.cntl TSYNC28/TSIG28 RSYNC27 RSER27 TCLK27/RSIG27.cntl TCLK27/RSIG27 TSER27 TSYNC27/TSIG27.cntl TSYNC27/TSIG27 RSYNC26 RSER26 TCLK26/RSIG26.cntl TCLK26/RSIG26 TSER26 TSYNC26/TSIG26.cntl TSYNC26/TSIG26 RSYNC25 RSER25 TCLK25/RSIG25.cntl TCLK25/RSIG25 TSER25 TSYNC25/TSIG25.cntl TSYNC25/TSIG25 RSYNC24 RSER24 TCLK24/RSIG24.cntl TCLK24/RSIG24 TSER24
Lead V9 W9 Y9 V10 U10 T10 W10 Y10 Y11 W11 V11 U11 Y12 W12 Y13 V12 T11 T12 U12 W13 Y14 Y15
I/O or Control Bit Description 0 = TCLK28/RSIG28 is an input 1 = TCLK28/RSIG28 is an output I/O I 0 = TSYNC28/TSIG28 is an input 1 = TSYNC28/TSIG28 is an output I/O O O 0 = TCLK27/RSIG27 is an input 1 = TCLK27/RSIG27 is an output I/O I 0 = TSYNC27/TSIG27 is an input 1 = TSYNC27/TSIG27 is an output I/O O O 0 = TCLK26/RSIG26 is an input 1 = TCLK26/RSIG26 is an output I/O I 0 = TSYNC26/TSIG26 is an input 1 = TSYNC26/TSIG26 is an output I/O O O 0 = TCLK25/RSIG25 is an input 1 = TCLK25/RSIG25 is an output I/O I 0 = TSYNC25/TSIG25 is an input 1 = TSYNC25/TSIG25 is an output I/O O O 0 = TCLK24/RSIG24 is an input 1 = TCLK24/RSIG24 is an output I/O I
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Bit 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
Symbol TSYNC24/TSIG24.cntl TSYNC24/TSIG24 RSYNC23 RSER23 TCLK23/RSIG23.cntl TCLK23/RSIG23 TSER23 TSYNC23/TSIG23.cntl TSYNC23/TSIG23 RSYNC22 RSER22 TCLK22/RSIG22.cntl TCLK22/RSIG22 TSER22 TSYNC22/TSIG22.cntl TSYNC22/TSIG22 RSYNC21 RSER21 TCLK21/RSIG21.cntl TCLK21/RSIG21 TSER21 TSYNC21/TSIG21.cntl TSYNC21/TSIG21 RSYNC20 RSER20 TCLK20/RSIG20.cntl TCLK20/RSIG20 TSER20 TSYNC20/TSIG20.cntl TSYNC20/TSIG20 RSYNC19 RSER19 TCLK19/RSIG19.cntl TCLK19/RSIG19 TSER19
Lead V13 T13 U13 W14 Y16 W15 V14 T14 U14 W16 V15 Y18 Y19 U15 Y20 W17 V16 W18 V17 U16 U17 T16 V18 W19 U18
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I/O or Control Bit Description 0 = TSYNC24/TSIG24 is an input 1 = TSYNC24/TSIG24 is an output I/O O O 0 = TCLK23/RSIG23 is an input 1 = TCLK23/RSIG23 is an output I/O I 0 = TSYNC23/TSIG23 is an input 1 = TSYNC23/TSIG23 is an output I/O O O 0 = TCLK22/RSIG22 is an input 1 = TCLK22/RSIG22 is an output I/O I 0 = TSYNC22/TSIG22 is an input 1 = TSYNC22/TSIG22 is an output I/O O O 0 = TCLK21/RSIG21 is an input 1 = TCLK21/RSIG21 is an output I/O I 0 = TSYNC21/TSIG21 is an input 1 = TSYNC21/TSIG21 is an output I/O O O 0 = TCLK20/RSIG20 is an input 1 = TCLK20/RSIG20 is an output I/O I 0 = TSYNC20/TSIG20 is an input 1 = TSYNC20/TSIG20 is an output I/O O O 0 = TCLK19/RSIG19 is an input 1 = TCLK19/RSIG19 is an output I/O I
DS3120
Bit 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191
Symbol TSYNC19/TSIG19.cntl TSYNC19/TSIG19 RSYNC18 RSER18 TCLK18/RSIG18.cntl TCLK18/RSIG18 TSER18 TSYNC18/TSIG18.cntl TSYNC18/TSIG18 RSYNC17 RSER17 TCLK17/RSIG17.cntl TCLK17/RSIG17 TSER17 TSYNC17/TSIG17.cntl TSYNC17/TSIG17 RSYNC16 RSER16 TCLK16/RSIG16.cntl TCLK16/RSIG16 TSER16 TSYNC16/TSIG16.cntl TSYNC16/TSIG16 RSYNC15 RSER15 TCLK15/RSIG15.cntl TCLK15/RSIG15 TSER15 TSYNC15/TSIG15.cntl TSYNC15/TSIG15 RSYNC14 RSER14 TCLK14/RSIG14.cntl TCLK14/RSIG14 TSER14
Lead V19 T17 T18 U19 W20 V20 R17 P16 R18 T19 U20 P17 R19 P18 T20 P19 N17 N16 N18 P20 N19 N20 M17 M16 M18
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I/O or Control Bit Description 0 = TSYNC19/TSIG19 is an input 1 = TSYNC19/TSIG19 is an output I/O O O 0 = TCLK18/RSIG18 is an input 1 = TCLK18/RSIG18 is an output I/O I 0 = TSYNC18/TSIG18 is an input 1 = TSYNC18/TSIG18 is an output I/O O O 0 = TCLK17/RSIG17 is an input 1 = TCLK17/RSIG17 is an output I/O I 0 = TSYNC17/TSIG17 is an input 1 = TSYNC17/TSIG17 is an output I/O O O 0 = TCLK16/RSIG16 is an input 1 = TCLK16/RSIG16 is an output I/O I 0 = TSYNC16/TSIG16 is an input 1 = TSYNC16/TSIG16 is an output I/O O O 0 = TCLK15/RSIG15 is an input 1 = TCLK15/RSIG15 is an output I/O I 0 = TSYNC15/TSIG15 is an input 1 = TSYNC15/TSIG15 is an output I/O O O 0 = TCLK14/RSIG14 is an input 1 = TCLK14/RSIG14 is an output I/O I
DS3120
Bit 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226
Symbol TSYNC14/TSIG14.cntl TSYNC14/TSIG14 RSYNC13 RSER13 TCLK13/RSIG13.cntl TCLK13/RSIG13 TSER13 TSYNC13/TSIG13.cntl TSYNC13/TSIG13 RSYNC12 RSER12 TCLK12/RSIG12.cntl TCLK12/RSIG12 TSER12 TSYNC12/TSIG12.cntl TSYNC12/TSIG12 RSYNC11 RSER11 TCLK11/RSIG11.cntl TCLK11/RSIG11 TSER11 TSYNC11/TSIG11.cntl TSYNC11/TSIG11 RSYNC10 RSER10 TCLK10/RSIG10.cntl TCLK10/RSIG10 TSER10 TSYNC10/TSIG10.cntl TSYNC10/TSIG10 RSYNC9 RSER9 TCLK9/RSIG9.cntl TCLK9/RSIG9 TSER9
Lead M19 M20 L17 L16 L18 L19 L20 K20 K19 K17 K18 J20 J19 J18 K16 J16 J17 H20 H19 G20 H18 H16 H17 F20 G19
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I/O or Control Bit Description 0 = TSYNC14/TSIG14 is an input 1 = TSYNC14/TSIG14 is an output I/O O O 0 = TCLK13/RSIG13 is an input 1 = TCLK13/RSIG13 is an output I/O I 0 = TSYNC13/TSIG13 is an input 1 = TSYNC13/TSIG13 is an output I/O O O 0 = TCLK12/RSIG12 is an input 1 = TCLK12/RSIG12 is an output I/O I 0 = TSYNC12/TSIG12 is an input 1 = TSYNC12/TSIG12 is an output I/O O O 0 = TCLK11/RSIG11 is an input 1 = TCLK11/RSIG11 is an output I/O I 0 = TSYNC11/TSIG11 is an input 1 = TSYNC11/TSIG11 is an output I/O O O 0 = TCLK10/RSIG10 is an input 1 = TCLK10/RSIG10 is an output I/O I 0 = TSYNC10/TSIG10 is an input 1 = TSYNC10/TSIG10 is an output I/O O O 0 = TCLK9/RSIG9 is an input 1 = TCLK9/RSIG9 is an output I/O I
DS3120
Bit 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261
Symbol TSYNC9/TSIG9.cntl TSYNC9/TSIG9 RSYNC8 RSER8 TCLK8/RSIG8.cntl TCLK8/RSIG8 TSER8 TSYNC8/TSIG8.cntl TSYNC8/TSIG8 RSYNC7 RSER7 TCLK7/RSIG7.cntl TCLK7/RSIG7 TSER7 TSYNC7/TSIG7.cntl TSYNC7/TSIG7 RSYNC6 RSER6 TCLK6/RSIG6.cntl TCLK6/RSIG6 TSER6 TSYNC6/TSIG6.cntl TSYNC6/TSIG6 RSYNC5 RSER5 TCLK5/RSIG5.cntl TCLK5/RSIG5 TSER5 TSYNC5/TSIG5.cntl TSYNC5/TSIG5 RSYNC4 RSER4 TCLK4/RSIG4.cntl TCLK4/RSIG4 TSER4
Lead G18 G16 G17 F19 D20 E19 F18 C20 F17 B20 D19 E18 E17 C19 C17 B19 B18 D16 C16 B17 A20 A19 E14 D15 A18
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I/O or Control Bit Description 0 = TSYNC9/TSIG9 is an input 1 = TSYNC9/TSIG9 is an output I/O O O 0 = TCLK8/RSIG8 is an input 1 = TCLK8/RSIG8 is an output I/O I 0 = TSYNC8/TSIG8 is an input 1 = TSYNC8/TSIG8 is an output I/O O O 0 = TCLK7/RSIG7 is an input 1 = TCLK7/RSIG7 is an output I/O I 0 = TSYNC7/TSIG7 is an input 1 = TSYNC7/TSIG7 is an output I/O O O 0 = TCLK6/RSIG6 is an input 1 = TCLK6/RSIG6 is an output I/O I 0 = TSYNC6/TSIG6 is an input 1 = TSYNC6/TSIG6 is an output I/O O O 0 = TCLK5/RSIG5 is an input 1 = TCLK5/RSIG5 is an output I/O I 0 = TSYNC5/TSIG5 is an input 1 = TSYNC5/TSIG5 is an output I/O O O 0 = TCLK4/RSIG4 is an input 1 = TCLK4/RSIG4 is an output I/O I
DS3120
Bit 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296
Symbol TSYNC4/TSIG4.cntl TSYNC4/TSIG4 RSYNC3 RSER3 TCLK3/RSIG3.cntl TCLK3/RSIG3 TSER3 TSYNC3/TSIG3.cntl TSYNC3/TSIG3 RSYNC2 RSER2 TCLK2/RSIG2.cntl TCLK2/RSIG2 TSER2 TSYNC2/TSIG2.cntl TSYNC2/TSIG2 RSYNC1 RSER1 TCLK1/RSIG1.cntl TCLK1/RSIG1 TSER1 TSYNC1/TSIG1.cntl TSYNC1/TSIG1 8MCLKO CLKSI CTCLK CTSYNC 8MSYNC 8MCLKI BTS WR*/(R/W*) RD*/(DS*) INT.cntl INT* BUS.cntl
Lead C15 B16 D14 A17 B15 C14 A16 D13 E13 B14 C13 A14 B13 D12 E12 A13 C12 B12 A12 D11 E11 C11 B11 A11 A10 B10 -
I/O or Control Bit Description 0 = TSYNC4/TSIG4 is an input 1 = TSYNC4/TSIG4 is an output I/O O O 0 = TCLK3/RSIG3 is an input 1 = TCLK3/RSIG3 is an output I/O I 0 = TSYNC3/TSIG3 is an input 1 = TSYNC3/TSIG3 is an output I/O O O 0 = TCLK2/RSIG2 is an input 1 = TCLK2/RSIG2 is an output I/O I 0 = TSYNC2/TSIG2 is an input 1 = TSYNC2/TSIG2 is an output I/O O O 0 = TCLK1/RSIG1 is an input 1 = TCLK1/RSIG1 is an output I/O I 0 = TSYNC1/TSIG1 is an input 1 = TSYNC1/TSIG1 is an output I/O O I I O I I I I I 0 = INT* is a zero ("0") 1 = INT* is 3-state ("z") O 0 = D0 to D7 or AD0 to AD7 is an input 1 = D0 to D7 or AD0 to AD7 is an output
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DS3120
Bit 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321
Symbol D0 or AD0 D1 or AD1 D2 or AD2 D3 or AD3 D4 or AD4 D5 or AD5 D6 or AD6 D7 or AD7 A0 A1 A2 A3 A4 A5 A6/ALE (AS) A7 FS0 FS1 FS2 FS3 FS4 CS* MUX FIACT* TEST
Lead D10 C10 A9 B9 C9 E10 E9 D9 A8 B8 A7 C8 E8 D8 A6 B7 C7 E7 D7 B6 A4 B5 C6 A3 D6
I/O or Control Bit Description I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I I I I I I
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DS3120
20.
TIMING DIAGRAMS
RECEIVE SIDE BOUNDARY TIMING Figure 20-1
RCLK
CHANNEL 23 CHANNEL 24
LSB MSB LSB F MSB
CHANNEL 1
RSER
RSYNC(1) RSYNC(2)
CHANNEL 23 CHANNEL 24
D/B A B C/A D/B
CHANNEL 1
A
RSIG
A
B
C/A
Notes:
1. RSYNC outputting an 8 kHz frame pulse (Modes 1, 3, 5, 7, 9, 10, and 12). 2. RSYNC outputting a "Gapped Clock" (Modes 2, 4, 6, 8, and 13).
TRANSMIT SIDE BOUNDARY TIMING Figure 20-2
TCLK
CHANNEL 1 CHANNEL 2
LSB MSB LSB MSB
TSER TSYNC / CTSYNC(1) TSYNC(2) TSYNC / CTSYNC(3)
LSB
F
MSB
CHANNEL 1
CHANNEL 2
B C/A D/B A B C/A D/B
TSIG
A
Notes:
1. TSYNC/CTSYNC is an 8 kHz frame boundary output (Modes 1, 3, 7, 9, 10, and 12). 2. TSYNC is an 8 kHZ frame boundary input (Mode 11). 3. TSYNC/CTSYNC is a "Gapped Clock" output (Modes 2, 4, 8, and 13).
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DS3120
8 MHZ INTERLEAVED BUS OPERATION (IBO) BYTE MODE TIMING Figure 20-3
8MSYNC
CHANNEL #
127
128
1
2
3
4
5
6
7
8
RSER
FR3 CH24 FR4 CH24 F
F
F
F
FR1 CH1
FR2 CH1
FR3 CH1
FR4 CH1
TSER(1)
FR3 CH24 FR4 CH24 F
F
F
F
FR1 CH1
FR2 CH1
FR3 CH1
FR4 CH1
RSIG(2)
FR3 CH24 FR4 CH24
FR1 CH1
FR2 CH1
FR3 CH1
FR4 CH1
TSIG(3)
FR3 CH24 FR4 CH24
FR1 CH1
FR2 CH1
FR3 CH1
FR4 CH1
BIT DETAIL
8MCLKI
8MSYNC
FRAMER 3, CHANNEL 24 FRAMER 4, CHANNEL 24
LSB F
RSER
LSB MSB
FRAMER 3, CHANNEL 24
FRAMER 4, CHANNEL 24
LSB F
TSER(1)
LSB MSB
FRAMER 3, CHANNEL 24
FRAMER 4, CHANNEL 24
A B C/D D/B
RSIG
A
B
C/A
D/B
FRAMER 3, CHANNEL 24
FRAMER 4, CHANNEL 24
A B C/D D/B
TSIG
A
B
C/A
D/B
Notes:
1. TSER will only sample the F bit position when the transmit formatter is in "transparent" mode. 2. RSIG contains robbed bit signaling data in the least significant nibble. 3. TSIG samples robbed bit signaling data in the least significant nibble.
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DS3120
8 MHZ INTERLEAVED BUS OPERATION (IBO) FRAME MODE TIMING Figure 20-4
8MSYNC
CHANNEL #
127
128
1
2
3
4
5
6
7
8
RSER
FR4 CH23 FR4 CH24 F
FR1 CH1
FR1 CH2
FR1 CH3
FR1 CH4
FR1 CH5
FR1 CH6
TSER(1)
FR4 CH23 FR4 CH24 F
FR1 CH1
FR1 CH2
FR1 CH3
FR1 CH4
FR1 CH5
FR1 CH6
RSIG(2)
FR4 CH23 FR4 CH24
FR1 CH1
FR1 CH2
FR1 CH3
FR1 CH4
FR1 CH5
FR1 CH6
TSIG(3)
FR4 CH23 FR4 CH24
FR1 CH1
FR1 CH2
FR1 CH3
FR1 CH4
FR1 CH5
FR1 CH6
BIT DETAIL
8MCLKI
8MSYNC
FRAMER 4, CHANNEL 23 FRAMER 4, CHANNEL 24
LSB F
RSER
LSB MSB
FRAMER 4, CHANNEL 23
FRAMER 4, CHANNEL 24
LSB F
TSER(1)
LSB MSB
FRAMER 4, CHANNEL 23
FRAMER 4, CHANNEL 24
A B C/D D/B
RSIG
A
B
C/A
D/B
FRAMER 4, CHANNEL 23
FRAMER 4, CHANNEL 24
A B C/D D/B
TSIG
A
B
C/A
D/B
Notes:
1. TSER will only sample the F bit position when the transmit formatter is in "transparent" mode. 2. RSIG contains robbed bit signaling data in the least significant nibble. 3. TSIG samples robbed bit signaling data in the least significant nibble.
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DS3120
DS3120 TRANSMIT DATA FLOW Figure 20-5
TSER TCBR1/2/3 0 HDLC Controller CCR4.1 CCR4.2 DS0 insertion enable (TDC1.7) TDC2 TDC1 4:0 TCBR1/2/3 1 TDC1.5 TCC1 to TCC3 IBCC TIR Function Select (CCR4.0) TCD 0 CCR3.1 TIDR 1 1 RSER Only Valid for "Loop Timed" Modes TIR1 to TIR3 In-Band Loop Code Generator TC1 to TC24 1 0 Per-Channel Code Generation 0 1 DS0 Source Mux 0 Hardware Signaling Insertion 1 TSIG
0 Idle Code / Per Channel LB 0 TS1 to TS12 1 Software Signaling Insertion
Software Signaling Enable (TCR1.4)
TTR1 to TTR3 Global Bit 7 Stuffing (TCR1.3) Bit 7 Zero Suppression Enable (TCR2.0) Frame Mode Select (CCR2.7) D4 Yellow Alarm Select (TCR2.1) Transmit Yellow (TCR1.0) BOC Controller TSER 1 1 0 BOC Enable (TBOC.7) 1 HDLC/BOC Enable (TBOC.6) TFDL Select (TCR1.2) 0 FDL Mux 0 F-Bit Pass Through (TCR1.6) F-Bit Mux 1 Frame Mode Select (CCR2.7) 0 0 TFDL D4 Bit 2 Yellow Alarm Insertion Bit 7 Stuffing
FPS or Ft Bit Insertion 0
1
Frame Mode Select (CCR2.7)
CRC Calculation 0 1 CRC Mux
CRC Pass Through (TCR1.5) Frame Mode Select (CCR2.7) D4 Yellow Alarm Select (TCR2.1) Transmit Yellow (TCR1.0) Frame Mode Select (CCR2.7) Transmit Yellow (TCR1.0) Pulse Density Enforcer Enable (CCR3.3) Pulse Density Violation (RIR2.0)
D4 12th Fs Bit Yellow Alarm Gen. ESF Yellow Alarm Gen. (00FF Hex in the FDL)
One's Density Monitor
KEY:
= Register = Device Pin = Selector Transmit Blue (TCR1.1) Blue Alarm Gen. TNRZ DS0 Monitor
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DS3120
21.
OPERATING PARAMETERS
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Non-Supply Pin Relative to Ground Core Supply Voltage (VDD_CORE) I/O Supply Voltage (VDD_IO) Operating Temperature for DS3120 Operating Temperature for DS3120N Storage Temperature Soldering Temperature -1.0V to +5.5V -0.3V to +1.98V -0.3V to +3.63V 0C to 70C -40C to +85C -55C to +125C See J-STD-020A
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (0C to 70C for DS3120; 0C to +85C for DS3120N)
PARAMETER Logic 1 Logic 0 Supply for the Core Supply for the IO Buffers SYMBOL VIH VIL VDD_CORE VDD_IO MIN 2.0 -0.3 1.71 2.97 TYP MAX 5.5 +0.8 1.89 3.63 UNITS V V V V NOTES
CAPACITANCE
PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP 5 7 MAX UNITS pF pF
(tA =25C)
NOTES
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DS3120
DC CHARACTERISTICS 0C to 70C; VDD_CORE = 1.71 to 1.89V & VDD_IO = 2.97 to 3.63V for DS3120 / -40C to +85C; VDD_CORE = 1.71 to 1.89V & VDD_IO = 2.97 to 3.63V for DS3120N
PARAMETER Supply Current for VDD_CORE = 1.8V Supply Current for VDD_IO = 3.3V Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V) SYMBOL IDDCORE MIN TYP 50 MAX UNITS mA NOTES 1
IDDIO IIL ILO IOH IOL -1.0 -1.0 +4.0
300 +1.0 1.0
mA A A mA mA
1 2 3
NOTES:
1. CTCLK = CLKSI = RCLK = 1.544 MHz operating in Mode 1; inputs tied low, outputs open circuited. 2. 0.0V < VIN < VDD_IO. 3. Applies to INT* / RSER / RSIG when 3-stated.
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DS3120
AC CHARACTERISTICS - MULTIPLEXED PARALLEL PORT (MUX = 1) 0C to 70C; VDD_CORE = 1.71 to 1.89V & VDD_IO = 2.97 to 3.63V for DS3120 / -40C to +85C; VDD_CORE = 1.71 to 1.89V & VDD_IO = 2.97 to 3.63V for DS3120N
PARAMETER Cycle Time Pulse Width, DS low or RD* high Pulse Width, DS high or RD* low Input Rise/Fall times R/W* Hold Time R/W* Set Up time before DS high CS*, FS0 to FS4 Set Up time before DS, WR* or RD* active CS*, FS0 to FS4 Hold time Read Data Hold time Write Data Hold time Muxed Address valid to AS or ALE fall Muxed Address Hold time Delay time DS, WR* or RD* to AS or ALE rise Pulse Width AS or ALE high Delay time, AS or ALE to DS, WR* or RD* Output Data Delay time from DS or RD* Data Set Up time SYMBOL t CYC PW EL PW EH tR,tF t RWH t RWS t CS MIN 200 100 100 20 10 50 20 TYP MAX UNITS ns ns ns ns ns ns ns NOTES
t CH t DHR t DHW t ASL t AHL t ASD PW ASH t ASED t DDR t DSW
0 10 0 15 10 20 30 10 20 50 80 50
ns ns ns ns ns ns ns ns ns ns
(see Figures 21-1 to 21-3 for details)
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DS3120
INTEL BUS READ AC TIMING (BTS=0 / MUX = 1) Figure 21-1
t CYC ALE t ASD WR*
PWASH tASED PW EH t CS t CH
t ASD
RD* CS* / FS0 to FS4
PWEL
t ASL AD0-AD7 t AHL
t DDR
t DHR
INTEL BUS WRITE TIMING (BTS=0 / MUX=1) Figure 21-2
t CYC ALE t ASD RD*
PWASH t ASED PWEH t CS t CH
t ASD
WR* CS* / FS0 to FS4
PWEL
t ASL AD0-AD7 t AHL t DSW
t DHW
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DS3120
MOTOROLA BUS AC TIMING (BTS = 1 / MUX = 1) Figure 21-3
PWASH AS t ASD DS PWEL t RWS R/W* AD0-AD7 (read) t ASL t AHL CS* / FS0 to FS4 AD0-AD7 (write) t ASL t AHL t DDR t DHR t CH t ASED t CYC t RWH PWEH
t CS t DSW
t DHW
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DS3120
AC CHARACTERISTICS - NON-MULTIPLEXED PARALLEL PORT (MUX = 0) 0C to 70C; VDD_CORE = 1.71 to 1.89V & VDD_IO = 2.97 to 3.63V for DS3120 / -40C to +85C; VDD_CORE = 1.71 to 1.89V & VDD_IO = 2.97 to 3.63V for DS3120N
PARAMETER Set Up Time for A0 to A7, FS0 to FS4 Valid to CS* Active Set Up Time for CS* Active to either RD*, WR*, or DS* Active Delay Time from either RD* or DS* Active to Data Valid Hold Time from either RD*, WR*, or DS* Inactive to CS* Inactive Hold Time from CS* Inactive to Data Bus 3- state Wait Time from either WR* or DS* Active to Latch Data Data Set Up Time to either WR* or DS* Inactive Data Hold Time from either WR* or DS* Inactive Address Hold from either WR* or DS* inactive SYMBOL t1 MIN 0 TYP MAX UNITS ns NOTES
t2
0
ns
t3
75
ns
t4
0
ns
t5
5
20
ns
t6
75
ns
t7
10
ns
t8
10
ns
t9
10
ns
See Figures 21-4 to 21-7 for details.
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DS3120
INTEL BUS READ AC TIMING (BTS=0 / MUX=0) Figure 21-4
A0 to A7 Address Valid
D0 to D7
Data Valid 5ns min. / 20ns max. t5
WR* CS* / FS0 to FS4
t1 0ns min. 0ns min. t2 t3 75ns max. t4 0ns min.
RD*
INTEL BUS WRITE AC TIMING (BTS=0 / MUX=0) Figure 21-5
t9 10ns min. A0 to A7 Address Valid
D0 to D7 t7 RD* CS* / FS0 to FS4 0ns min. WR* t1 0ns min. t2 t6 75ns min. t4 0ns min. 10ns 10ns min. min. t8
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DS3120
MOTOROLA BUS READ AC TIMING (BTS=1 / MUX=0) Figure 21-6
A0 to A7 Address Valid
D0 to D7
Data Valid 5ns min. / 20ns max. t5
R/W* CS* / FS0 to FS4
t1 0ns min. 0ns min. t2 t3 75ns max. t4 0ns min.
DS*
MOTOROLA BUS WRITE AC TIMING (BTS=1 / MUX=0) Figure 21-7
t9 10ns min. A0 to A7 Address Valid
D0 to D7 10ns min. t1 0ns min. t2 t6 75ns min. DS* t4 0ns min. t7 t8 10ns min.
R/W* CS* / FS0 to FS4
0ns min.
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DS3120
AC CHARACTERISTICS - RECEIVE SIDE 0C to 70C; VDD_CORE = 1.71 to 1.89V & VDD_IO = 2.97 to 3.63V for DS3120 / -40C to +85C; VDD_CORE = 1.71 to 1.89V & VDD_IO = 2.97 to 3.63V for DS3120N
PARAMETER RCLK Period RCLK Pulse Width RNRZ Set Up to RCLK Falling RNRZ Hold From RCLK Falling RCLK Rise and Fall Times Delay RCLK to RSER or RSIG Valid Delay RCLK to RSYNC See Figure 21-8 for details. SYMBO L t CP t CH t CL t SU t HD tR,tF t D1 t D2 MIN TYP 648 75 75 20 20 25 50 50 MAX UNITS ns ns ns ns ns ns ns ns NOTES
RECEIVE SIDE AC TIMING Figure 21-8
tR RCLK t SU RNRZ t D1 RSER / RSIG Bit 192 t RSYNC D2 Bit 0 t HD Bit 1 Bit 2 t CP tF t CL t CH
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DS3120
AC CHARACTERISTICS - 8 MHZ INTERLEAVED BUS OPERATION (IBO) 0C to 70C; VDD_CORE = 1.71 to 1.89V & VDD_IO = 2.97 to 3.63V for DS3120 / -40C to +85C; VDD_CORE = 1.71 to 1.89V & VDD_IO = 2.97 to 3.63V for DS3120N
PARAMETER 8MCLKI Period RCLK Pulse Width 8MSYNC Set Up to 8MCLKI Falling 8MSYNC Hold from 8MCLKI Falling TSER / TSIG Set Up to RCLK Falling TSER / TSIG Hold From RCLK Falling 8MCLKI Rise and Fall Times Delay 8MCLKI to RSER or RSIG Valid Delay 8MCLKI to CTSYNC See Figure 21-9 for details. SYMBOL t CP t CH t CL t SU t HD t SU t HD tR,tF t D1 t D2 MIN 50 50 20 20 20 20 10 50 50 TYP 122 MAX UNITS ns ns ns ns ns ns ns ns ns ns NOTES
t CH -5 infinite
8 MHZ IBO AC TIMING Figure 21-9
tR 8MCLKI t SU TSER / TSIG t D1 RSER / RSIG Bit 1023 t 8MSYNC t CTSYNC D2 SU Bit 0 t HD t HD Bit 1 Bit 2 t CP tF t CL t CH
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DS3120
AC CHARACTERISTICS - TRANSMIT SIDE 0C to 70C; VDD_CORE = 1.71 to 1.89V & VDD_IO = 2.97 to 3.63V for DS3120 / -40C to +85C; VDD_CORE = 1.71 to 1.89V & VDD_IO = 2.97 to 3.63V for DS3120N
PARAMETER TCLK Period TCLK Pulse Width TSYNC Set Up to TCLK Falling TSYNC Hold from TCLK Falling TSER / TSIG Set Up to TCLK or CTCLK Falling TSER / TSIG Hold from TCLK or CTCLK Falling TCLK Rise and Fall Times Delay TCLK/CTCLK to TNRZ Valid Delay TCLK/CTCLK to TSYNC or CTSYNC See Figure 21-10 for details. SYMBO L t CP t CH t CL t SU t HD t SU t HD tR,tF t D1 t D2 MIN TYP 648 75 75 20 20 20 20 25 50 50 MAX UNITS ns ns ns ns ns ns ns ns ns ns 1 NOTES 1 1 1, 2 1, 2
t CH -5 infinite
3
NOTES:
1. TCLK is an input (Modes 11, 12, or 13). 2. TSYNC is an input (Mode 11 only). 3. TSYNC is an output (Modes 1 to 4 or 12 or 13).
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DS3120
TRANSMIT SIDE AC TIMING Figure 21-10
tR TCLK(1) / CTCLK t SU TSER / TSIG t D1 TNRZ Bit 192 t TSYNC(2) t TSYNC(3) / CTSYNC D2 SU Bit 0 t HD t HD Bit 1 Bit 2 t CP tF t CL t CH
AC CHARACTERISTICS - JTAG TEST PORT INTERFACE 0C to 70C; VDD_CORE = 1.71 to 1.89V & VDD_IO = 2.97 to 3.63V for DS3120 / -40C to +85C; VDD_CORE = 1.71 to 1.89V & VDD_IO = 2.97 to 3.63V for DS3120N
PARAMETER JTCLK Period JTCLK Clock Low Time JTCLK Clock High Time JTMS / JTDI Set Up Time to JTCLK Rising JTMS / JTDI Hold Time from JTCLK Rising Delay Time from JTCLK Falling to JTDO Valid See Figure 21-11 for details. SYMBOL t1 t2 t3 t4 t5 t6 MIN 1000 400 400 50 50 2 50 TYP MAX UNITS ns ns ns ns ns ns NOTES
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DS3120
JTAG TEST PORT AC TIMING Figure 21-11
t1 t2 JTCLK t4 JTMS / JTDI t6 JTDO t5 t3
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DS3120
22.
MECHANICAL PACKAGE SPECIFICATIONS
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